UVM_RAL: Why Predictor calling bus2reg function(Adapter) 2 times automatically?

UVM
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3

In reply to chr_sue:

Please find the attached Snippets

ENV Class:

Declaration : 	uvm_reg_predictor #(apb_seq_item) nvme_reg_predictor; 

   if (m_env_cfg.m_apb_agent_cfg.active == UVM_ACTIVE) begin
       reg2apb = apb_reg_adapter::type_id::create ("reg2apb");
	if (m_env_cfg.m_apb_rm.get_parent() == null) begin
	   m_env_cfg.m_apb_rm.apb_reg_top_block_map.set_sequencer (m_apb_agent.m_sequencer, reg2apb);
	end
		my_reg_predictor.map     = m_env_cfg.m_apb_rm.apb_reg_top_block_map;
		my_reg_predictor.adapter = reg2apb;
		m_env_cfg.m_apb_rm.apb_reg_top_block_map.set_auto_predict(0);
		m_apb_agent.m_monitor.apb_ap.connect(my_reg_predictor.bus_in);
   end

TEST Class:


	phase.raise_objection (this, "REG_Test started");
	  begin
		apb_reg_wr_rd_seq_h = apb_reg_wr_rd_seq::type_id::create("apb_reg_wr_rd_seq_h");
		apb_reg_wr_rd_seq_h.start (null);
		#100ns;
	  end 
	phase.drop_objection (this, "REG_Test finished");

Sequence Class:


   Declaration :
	apb_reg_top_block  model; 
	nvme_env_config    m_env_cfg; 
  
	uvm_reg_data_t     read_data;  
	uvm_reg_data_t     rd_data;

   _Task Body:_
	write_reg(model.CAP_LOW,status,32'hFFFF_FFFF);
	read_reg(model.CAP_LOW,status,read_data);
	if(status == UVM_NOT_OK)
	  `uvm_error("REG_SEQUENCE","Status Is NOT OK During Read Operation")
	rd_data = model.CAP_LOW.get_mirrored_value();

	if(rd_data != read_data) begin
	  `uvm_error("APB_REG_SEQUENCE","^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^")
	  `uvm_error("APB_REG_SEQUENCE","^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^")
	  `uvm_error("APB_REG_SEQUENCE"," The Compared Value of Mirrored and Register Read is Wrong ")
	  `uvm_error("APB_REG_SEQUENCE","^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^")
	  `uvm_error("APB_REG_SEQUENCE","^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^")
	end