[UVM RAL] how to exclude some registers in the register test

UVM
1

I have one SoC register module in my RAL case.
In my test case, I started the sequence of uvm_reg_hw_reset_seq, uvm_reg_bit_bash_seq, uvm_reg_access_req.
Some registers are used for reset/clk control, if they are disabled, many other registers will unable to access. for example, SCU.SWEN, SCU.SWRST, BLK1.SWEN, BLK2.SWEN.
I have a initial process to set these reset/clk control registers before I start the uvm_reg seqeunce.
My question is, How can I exclude these control registers during the UVM register test ?
because once the control registers are disabled, many other register read/write access will be blocked in the DUT.

2

In reply to jacobi:

Hello, there could be multiple ways you can achieve the same results:

  1. by default the uvm reg sequences have a special continue check mechanism used in the body where they check if the specific uvm reg has the flag uvm_no_[ral_test,ral_write_test] if those flags are set to 1 then it will continue from the for each used to run through all the registers in the specific map. By setting and unsetting those you can exclude and then include back again the registers.
  2. you can create your own file listing the registers you wanna exclude and then before starting the sequence you simply call the exclusion method
  3. you can use the set compare alternatively to avoid checking with the mirror but as far I can understand from your concerns the tax should never start if you are not targeting the register is that correct ?
  4. lastly you can extend the uvm the sequence and then pass the registers you do not wanna touch, surely it make it less reusable but maybe you can always customize it to make suitably for many scenarios.

Hope this helps you. Regards

3

In reply to Rsignori92:

Thanks, I select the option 1, use uvm_resource_db to set the register or block “NO_REG_HW_RESET_TEST” or “NO_REG_TESTS” to 1.
But, I have to re-compile the env.
The best way is using one config file in run time and do not need the re-compile.

4

In reply to jacobi:

How can I pass uvm_resourse_db as runtime argument in a config file. Is it tool specific?