UVM RAL - different bit width for frontdoor and backdoor access

Hi guys.
I have a memory where each word consists of 32-bit data + 7-bit ECC. This memory is connected to 32-bit AHB bus and only data bits are available via this bus.
I want to access this memory using UVM RAL where:

  • frontdoor access will be translated to a single 32-bit access via AHB
  • backdoor access will allow to read/write all 39 bits (data+ECC)

How to achieve such behavior? When I set the memory bit width to 32 bits, I cannot reach ECC bits via backdoor. When I put the memory bit width to 39 bits, each frontdoor access is translated into two AHB transactions on successive addresses.