UVM RAL : combining byte addressing RAL with word addressing RAL

We are in situation our IP has byte addressing.
i.e
Address 32bit 0x01 byte 1
Address 32bit 0x02 byte 2

Where one of the subsystem we integrating to word addressing
i.e
Address 32bit 0x01 32bit data 1
Address 32bit 0x02 32bit data 2

the RTL team took care of this

When we integrating the RAL
We added IP reg model to subsystem reg model using

m_subsystem_model.add_submap(m_ip_regblock,m_offset);

But this does not work alone, we need to right shift address while accessing our IP
Is there any UVM construct available so that UVM RAL automatically dose this right shift.

The solution we are using now
In reg_adaptor we are shifting address if the address falls under our IP range.

Any help would be appreciated. thanks