In reply to chr_sue:
Hi, thank you for your replay.
Yes, reg2 is one 24 bit register distributed over 3 addresses. The same reg3.
reg2 contains only one bit, and it is presented as 8 bit distributed over one address.
(pseudo code)
class reg0 extends uvm_reg;
`uvm_object_utils(reg0)
rand uvm_reg_field f0;
function new(string name = “reg0”);
super.new(name, 8, UVM_NO_COVERAGE);
endfunction
virtual function void build();
f0 = uvm_reg_field::type_id::create(“f0”);
f0.configure(this, 8, 0, “RW”, 0, 0, 1, 1, 0);
endfunction
endclass : reg0
class reg1 extends uvm_reg;
`uvm_object_utils(reg1)
rand uvm_reg_field f0;
function new(string name = “reg1”);
super.new(name, 8, UVM_NO_COVERAGE);
endfunction
virtual function void build();
f0 = uvm_reg_field::type_id::create(“f0”);
f0.configure(this, 1, 0, “RW”, 0, 0, 1, 1, 0);
endfunction
endclass : reg1
class reg2 extends uvm_reg;
`uvm_object_utils(reg2)
rand uvm_reg_field f0;
function new(string name = “reg2”);
super.new(name, 24, UVM_NO_COVERAGE);
endfunction
virtual function void build();
f0 = uvm_reg_field::type_id::create(“f0”);
f0.configure(this, 24, 0, “RW”, 0, 0, 1, 1, 0);
endfunction
endclass : reg2
class reg3 extends uvm_reg;
`uvm_object_utils(reg3)
rand uvm_reg_field f0;
function new(string name = “reg3”);
super.new(name, 24, UVM_NO_COVERAGE);
endfunction
virtual function void build();
f0 = uvm_reg_field::type_id::create(“f0”);
f0.configure(this, 24, 0, “RW”, 0, 0, 1, 1, 0);
endfunction
endclass : reg3
…
bus_map = create_map(“bus_map”, 'h00, 4, UVM_LITTLE_ENDIAN);
…
bus_map.add_reg(reg0_inst, 'h00, “RW”);
bus_map.add_reg(reg1_inst, 'h01, “RW”);
bus_map.add_reg(reg2_inst, 'h02, “RW”);
bus_map.add_reg(reg3_inst, 'h05, “RW”);
I am trying to implement RAL for the existing registers with various widths. Some of them are 53 bit or 304 bit, hundreds of them, all diverse. I use one bus_map with n_bytes 4 which is aligned with ahb interface of 32bits.
When I have, for example, one 24 bit register, instead of 32 bit access that RAL does automatically, my idea is to implement pre-write() callback in order to modify RAL default behavior.
For one 24 bit register, in pre-write() I would like to overwrite information, using n_bits (of uvm_reg_item) and to tell to adapter: if n_bits = 24 => write 16bits on addresses 0x02 and 0x03, and 8bits on address 0x04.
Thank you!