UVM Raising Objection

UVM
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Q1) iam still a beginner at UVM, i want to know why we are using the raise objection?
does it related to the run_phase of the components as all the run phases run in parallel , so the objection mechanism make them like run in Series?

and i saw 2 ways of raising objections some putting the raise objection inside the sequence class and some putting it inside the test class what is the difference between these ways?

Q2) also i have read that when we call raise objection we set a count to 1 and this count have to increase when we use raise objection again.
the above sentence will help me when iam using alot of raising objection in my test bench right ?

Thanks.

2

In reply to le_NOIRE2000:

All the run_phase tasks of all components run in parallel. Some run_phases execute in forever loops (like those in monitors). But without an objection, the run_phase ends and terminates all tasks in zero time. You raise an objection on certain components, like the top-level test component that indicates that particular component must lower its objection indicating the test is over.