In reply to cuonghl:
The UVM testbench is un-timed and nothing should be considered to take ‘too long’. As Chris mentioned, the register reads/writes generate sequence items. These sequence items will take time to process through the sequencer (as they will be arbitrated with the other sequence items), and the bus protocol will take time. It is only when the transaction is complete per the monitor that the register predictor will see the read/write.
However, these delays shouldn’t affect the behavior of the testbench. If you are waiting on a specific register value, you should be polling that register, just like the software will.