In reply to cuonghl:
Without looking at the code, it is tough to determine where the delay is coming from. Just a few thoughts:
- Is the monitor,
- capturing the write transactions right on time as per the protocol?
- waiting for some event or condition before writing into analysis port (that is connected to adapter)?
- Is the adapter adding any delays instead of just converting the bus2reg transaction?
- Is the predictor taking time to update the register map, even if it gets a REG WRITE transaction from adapter?