In reply to dave_59:
I spent good amount of time in debugging, analysing and going through below info:
http://www.sunburst-design.com/papers/CummingsSNUG2016AUS_VerificationTimingTesting.pdf
I changed my code as below and things are working.
**But i have a question:
**
I added below line before sampling the DUT outputs.
@(posedge counter_vif.monitor_cb);
**Will not above line add a clock cycle delay? what exactly does it do? please let me know.
**
virtual task run_phase(uvm_phase phase);
super.run_phase(phase);
forever begin
@(posedge counter_vif.clk);
if (counter_vif.clk_en && counter_vif.reset == 1) begin
seq_item_collected.count_value = counter_vif.count_value;
seq_item_collected.load_counter = counter_vif.load_counter;
seq_item_collected.up_counter = counter_vif.up_counter;
// Sample DUT outputs with monitor clock
@(posedge counter_vif.monitor_cb);
seq_item_collected.current_value = counter_vif.current_value;
seq_item_collected.count_reached = counter_vif.count_reached;
seq_item_collected.sprint();
trans_collected_port.write(seq_item_collected)
end //
end //forever
endtask : run_phase