UVM_MEM with Write Only access

UVM
,
3

In the source code of the uvm_mem configure function you can find this code:


   if (m_access != "RW" && m_access != "RO") begin
      `uvm_error("RegModel", {"Memory '",get_full_name(),"' can only be RW or RO"})
      m_access = "RW";
   end

And the documentation of get_rights is:

// Function: get_rights
   //
   // Returns the access rights of this memory.
   //
   // Returns "RW", "RO" or "WO".
   // The access rights of a memory is always "RW",
   // unless it is a shared memory
   // with access restriction in a particular address map.
   //
   // If no address map is specified and the memory is mapped in only one
   // address map, that address map is used. If the memory is mapped
   // in more than one address map, the default address map of the
   // parent block is used.
   //
   // If an address map is specified and
   // the memory is not mapped in the specified
   // address map, an error message is issued
   // and "RW" is returned. 
   //