I am looking for insight into alternate uvm_mem frontdoor techniques for SRAMs that can be accessed from 4 different busses; 2-AHB, 2-AXI. The set_frontdoor() sequence registration method looks promising but I can’t find an example in my Academy or Web searches so am hesitant to pursue it or spend significant time on it.
My basic problem is that I want to test frontdoor accesses to all the SRAMs and the width of the AHB WDATA[31:0] is smaller than the width of my SRAM rows. The latter can be as big as [323:0] with parity. The base code recognizes the size of the SRAM via n_bits,m_n_bits, …etc, so I am unable to do just a 4-byte write or read. Once do_write(), do_bus_write() get involved multiple 4-byte write/read cmds are driven onto AHB to fill the entire SRAM row.
I’ve dug through the code to see that if a frontdoor sequence is defined then that sequence intercepts the write. Anyone have experience or example code of how to use the frontdoor? Or another method?