Does anyone know if uvm_mem have mirror model like uvm_reg_model?
I want to use the expected memory value without accessing (backdoor or frontdoor) of the actual RTL, in my scoreboards.
In reply to Eranr:
For uvm_mem there is no mirror in the UVM testbench, because it would explode.
See the mechanisms in the UVM User Guide and in the Verification Academy Code examples (https://verificationacademy.com/cookbook/cookbook-code-examples#UVM_Examples:#UVM_Examples:#UVM_Examples:)
In reply to chr_sue:
Hi, So if I want to just use the uvm_mem feature of RAL and I dont have any memory being defined in DUT, can this still be used. Because once I write in the memory and try to read back, it is reading the value as 0s and not what I have written.
Will this approach work, or should I use only the system verilog (memories, i.e. queues or associative arrays etc).
In reply to Sindhuja_Rao:
The main use of uvm_mem is the RAL memory mapping feature which maps a name to a physical address and a particular driver interface. If you don’t need that, then there’s a little value
In reply to dave_59:
So If I dont have the physical memory in my DUT then having a RAL memory just to use the feature of mem, is not needed. Instead of this I can go for normal System verilog memory feature.? Am I correct?
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