In reply to sarth21:
Due to the nature of hardware design, a typical UVM testbench will create a large number of dynamic parallel processes. Most of these processes are very small in nature, and attempting to create a new CPU thread for each process and synchronize these threads would create so much overhead that it isn’t worth it. This is why the typical UVM/SV simulator is not multi-threaded.
There are ways to simulate RTL using multiple threads, but since RTL is static in nature, it is easier to control the number of parallel threads.