I was able to do this before in a similar fashion and have looked for all the possible connections right from the testbench to the driver and all the components in my environment are set up correctly. Is there any method to debug this issue further inside the UVM libraries to dig further into the problem?
The hierarchy string you are providing should be same as the string name you have provided while creating components. Also check by raising an objection in the sequence as shown below
I tried that but it didn’t work for me. I have tried many things but unable to pinpoint the problem that’s why I asked for a way to isolate and debug the issue.
The hierarchy string you are providing should be same as the string name you have provided while creating components. Also check by raising an objection in the sequence as shown below
If I place a breakpoint inside the sequence body task, my simulation finishes without hitting it. I assume anything placed inside the body won’t get executed, right? I have checked the hierarchy string and it matches the component instance names.
looking closely into the transcript of my test I found this.
UVM_WARNING verilog_src/uvm-1.2/src/base/uvm_traversal.svh(267) @ 0: reporter [UVM/COMP/NAME] the name "ap_egrs_agnt " of the component "uvm_test_top.env.ap_egrs_agnt " violates the uvm component name constraints.
Turns out there was an extra space at the end of the string I passed while creating the object for the agent. Issue resolved, thanks for the support.