UVM ERROR

UVM
,
1

Hi, I am getting this error in the code below. Can anybody help me resolve this error?
Error-[SE] Syntax error
Following verilog source has syntax error :
“/root/Downloads/Soc-DV/dv/uvm_agents/jtag_agent/jtag_driver.sv”, 39: token
is ‘logic’
logic [4:0] data;
^
System verilog keyword ‘logic’ is not expected to be used in this context.

 task drv_action(input jtag_sequence_item seq_item  );
    jtag_if.wait_clks(9);
    jtag_if.wait_clks_neg(1);
    logic [4:0] data;
    case (seq_item.action)
        JTAG_SEQ_ITEM_ACTION_SYNC_RESET: begin
          data = 5'h1f;
          //`uvm_info(get_name(), "Synchronous Reset", UVM_NONE)
          //logic [4:0] data;
          for (int i=0; i<$size(data); i++ ) begin
              jtag_if.TMS <= data[i];
              jtag_if.wait_clks_neg(1);
          end
        end
        JTAG_SEQ_ITEM_ACTION_SHIFT_IR: begin
          `uvm_info(get_name(), "shift-IR", UVM_NONE)         
        end
      endcase
      `uvm_info(get_name(), "reset sequence has been sent to the interface", UVM_NONE)
  endtask
2

In reply to Rana Adeel Ahmad:

Per the LRM, all variables must be declared prior to procedural statements. You need to move the declaration of ‘data’ to the beginning of the task.