HI ,
While running the reset sequence , i am facing uvm error.
Error::
The task responsible for requesting a wait_for_grant on sequencer ‘uvm_test_top.SysEnv.AHBAgent.ahbSqr0’ for sequence ‘uvm_test_top.SysEnv.Agent.ahbSqr0.ahbSeqRdRegular’ has been killed, to avoid a deadlock the sequence will be removed from the arbitration queue.
please help me find any issue with sequence body. Note:: i have pasted the body of the sequence, please ignore any macros or defines.
// ---------------------------------------------------------------------------
// body()
// ---------------------------------------------------------------------------
task cTestResetSeq::body();
string myname = "cTestResetSeq";
`cri_uvm_info(1, $sformatf("[%0s] -------------------------------------------- ", myname))
`cri_uvm_info(1, $sformatf("[%0s] ------- Starting cTestResetSeq ------- ", myname))
`cri_uvm_info(1, $sformatf("[%0s] -------------------------------------------- ", myname))
foreach (StatesToReset[ii]) begin
BasicTestSeq = null;
ErrWrongCipherSeq = null;
fork
begin : Seq1
if (StatesToReset[ii] == STATUS_ERROR) begin
// we have to call a sequence that exercises error
`uvm_create(ErrWrongCipherSeq)
`cri_randomize(ErrWrongCipherSeq, with {
BusPriv == local::BusPriv;
BusMaster == local::BusMaster;})
`cri_uvm_info(`DEBUG_LOW, $sformatf("[%0s] Calling a new error sequence.", myname))
`uvm_send(ErrWrongCipherSeq)
end
else begin
assert(ShaOperation.randomize() with {
Command != CONTROL_COMMAND_KEY;});
`uvm_create(BasicTestSeq)
`cri_randomize(BasicTestSeq, with {
BusPriv == local::BusPriv;
BusMaster == local::BusMaster;
Command == ShaOperation.Command;
CipherOp == ShaOperation.Cipher;
NumKeys == 1;
NumRequests == 2;})
`cri_uvm_info(`DEBUG_LOW, $sformatf("[%0s] Calling a new test sequence.", myname))
`uvm_send(BasicTestSeq)
end
end
begin : resetSeq
automatic int timeout = 0;
`cri_uvm_info(`DEBUG_LOW, $sformatf("[%0s] Waiting for state %s to reset core",
myname, fStatusStr(StatesToReset[ii])))
if ($test$plusargs("TEST_SEQ1")) begin
while (MainInf.StatusReg[STATUS_REG_Status_SRANGE] !== StatesToReset[ii]) begin
@(negedge MainInf.clk);
timeout++;
if (timeout == 10000) begin
`cri_uvm_fatal(this.get_name(), $sformatf("State %s never happened in 10000 cycles.",
fStatusStr(StatesToReset[ii])))
end
end
end
else begin
while (MainInf.StatusReg[STATUS_REG_Status_SRANGE] !== StatesToReset[ii]) begin
@(negedge MainInf.clk);
timeout++;
if (timeout == 10000) begin
`cri_uvm_fatal(this.get_name(), $sformatf("State %s never happened in 10000 cycles.",
fStatusStr(StatesToReset[ii])))
end
end
end
`cri_uvm_info(`DEBUG_LOW, $sformatf("[%0s] Core will be reset during %s state.",
myname, fStatusStr(StatesToReset[ii])))
SysEnv.ResetInjector.tApplyReset();
super.tSetupIPa();
// stop concurrent thread
disable Seq1;
if (StatesToReset[ii] == STATUS_ERROR) begin
// Kill ErrWrongCipherSeq
while (ErrWrongCipherSeq == null) begin
@(negedge MainInf.clk);
end
ErrWrongCipherSeq.kill();
end
else begin
// Kill BasicTestSeq
while (BasicTestSeq == null) begin
@(negedge MainInf.clk);
end
BasicTestSeq.kill();
end
end
join
// Wait for reset to finish
repeat(50) @(negedge MainInf.clk);
// Poll for STATUS_AVAILABLE
`uvm_create(PollSeq)
`cri_randomize(PollSeq, with {
BusPriv == local::BusPriv;
BusMaster == local::BusMaster;
RegAddr == StatusReg.addr;
ExpectedReadData == STATUS_AVAILABLE;
Mask == 32'hff;})
`cri_uvm_info(`DEBUG_LOW, $sformatf("[%0s] After reset, poll for status AVAILABLE.", myname))
`uvm_send(PollSeq)
wait fork;
end
`cri_uvm_info(1, $sformatf("[%0s] --------------------------------------------- ", myname))
`cri_uvm_info(1, $sformatf("[%0s] ------- Done cTestResetSeq ------------ ", myname))
`cri_uvm_info(1, $sformatf("[%0s] --------------------------------------------- ", myname))
endtask : body