Hi ,
I want to get uvm_error and uvm_info instead of errors from assertion.
Can i use uvm_error or info in system verilog interface ?
Thanks
Senkadir
Hi ,
I want to get uvm_error and uvm_info instead of errors from assertion.
Can i use uvm_error or info in system verilog interface ?
Thanks
Senkadir
Yes. Just import uvm_pkg::#; and include "uvm_macros.svh" in your interface, and use
uvm_error in the fail action of your assertion.
In reply to dave_59:
I tried the solution , but does not work when i don’t use it in else part .
I don’t know why . But it works when assertion fails and triggers an uvm_error.
I wanted some `uvm_info statements before i assert the property and it fails.
Thanks
Senkadir
In reply to senkadirrajasekaran:
I don’t know what you mean by
I wanted some `uvm_info statements before i assert the property and it fails.
If these are concurrent assertions, what do you mean by before? Show some examples.