UVM Error : The definition for the forward-referenced interface

UVM
, ,
1

Hi,

I am facing trouble in compiling my UVM code .I am seeing the below error.

Error Message :

Error-[SV-UIOT] Undefined interface or type
tb/monitor.sv, 6
fifoPorts, “itf”
The definition for the forward-referenced interface ‘fifoPorts’ is missing
or ‘fifoPorts’ is the name of an undefined user type.
Check to see if the interface definition file/work library is missing or the
definition of the user type is missing.

Error-[SV-UIOT] Undefined interface or type
tb/monitor.sv, 25
fifoPorts, “anonymous_type”
The definition for the forward-referenced interface ‘fifoPorts’ is missing
or ‘fifoPorts’ is the name of an undefined user type.
Check to see if the interface definition file/work library is missing or the
definition of the user type is missing.

1 warning
2 errors

Interface code :
interface fifoPorts #(parameter DSIZE = 8);

logic [DSIZE-1:0] rdata;
logic wfull;
logic rempty;
logic [DSIZE-1:0] wdata;
logic winc, wclk, wrst_n;
logic rinc, rclk, rrst_n;

endinterface

Monitor Code ( Highlighted the code that is giving me error )

class monitor extends uvm_monitor;
`uvm_component_utils(monitor)

virtual interface fifoPorts itf;
seqItem wtrans, rtrans;
uvm_analysis_port #(seqItem) readDataSend_port;
uvm_analysis_port #(seqItem) writeDataSend_port;

// This parameter controls the number of rclk cycles, after which the read data appear to FIFO output
int readDataReady = 1;
int writeDataReady = 1;

int fifo_DEPTH; // This variable contains FIFO depth, neede to check if fifo is full or empty
int numbOfWritesInFifo;	

function new (string name="monitor", uvm_component parent);
	super.new(name, parent);
	this.numbOfWritesInFifo = 0;
endfunction

function void build_phase (uvm_phase phase);
   **uvm_config_db #(virtual fifoPorts)::get(this, " * ","itf", itf);**
   
	readDataSend_port = new("readDataSend_port",this);
	writeDataSend_port = new ("writeDataSend_port", this);
	wtrans = seqItem::type_id::create("wtrans", this);
	rtrans = seqItem::type_id::create("rtrans", this);
  **uvm_config_db #(int)::get(null, " * ","DEPTH", fifo_DEPTH);**
endfunction

Can any one please tel me what does the error mean and how to solve this issue .

2

In reply to ritheshraj:

The declaration of your virtual interface handle in your monitor is incorrect. You don’t add the keyword ‘interface’.

You want:


virtual fifoPorts itf;
3

In reply to cgales:

Hi , I did the above change which you mentioned but I am seeing different issue now .

**Error-[SE] Syntax error
Following verilog source has syntax error :
“fifoPorts.sv”, 3: token is ‘fifoPorts’
interface fifoPorts #(parameter DSIZE = 8);
^
**

4

In reply to ritheshraj:

The interface code you posted compiles fine.

If you get an error in the first line of code of a file, you should take a look at the previous file in your compilation command. Are you missing an endclass somewhere?