Uvm_do copy method

UVM
, ,
1 
class a;
endclass

class b extends a;
 
  int k=20;
  function hi(a a_h);
     b b3_h;
    $cast(b3_h,a_h);
    $display(b3_h.k);
    
  endfunction
endclass

module hi;
  b b1_h,b2_h;
  
  initial begin
    b1_h=new();
    b2_h=new();
    b1_h.hi(b2_h);
  end
  
endmodule

Here, we are pointing parent handle to child inside function argument and if we try to aceess child variables, it is not possible. But if we create another child object inside function and do casting,i.e, pointing that child handle to parent handle,then we access the earlier child VARIABLES.it is same concept that we use in uvm_do copy method.why is it happening so?what is the theroy behind?

2

In reply to james333:

The parent and child relationship should only apply to the topology of the environment. When discussing inheritance, you should use the terms base class and extended class. This differentiation can significantly help when describing your issue.

Typically, the base class (class ‘a’ in your example) will have all the required functions defined. In this case, the function ‘hi’ would be defined in class ‘a’, and since class ‘a’ only knows the definition of class ‘a’, it would have the input argument of class ‘a’.

When you extend class ‘a’, SystemVerilog requires that all extended functions have the same arguments, so in class ‘b’, the function ‘hi’ requires class ‘a’ as an argument. However, to access any additional variables in the extended class ‘b’, you need to use $cast().

Since do_copy() is defined in the base class uvm_object(), you are required to use the same function prototype and $cast() to your specific class.