Uvm_declare_p_sequencer throwing warning and related error

UVM
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1

Hello,

Please find the code snippets for sequencer and sequence I am using

class my_sequencer extends uvm_sequencer#(my_packet);

`uvm_component_utils(my_sequencer)

my_uvc_cfg uvc_cfg;

function new(string name = “my_sequencer”, uvm_component parent);
super.new(name,parent);
endfunction : new

virtual function void build_phase(uvm_phase phase);
super.build_phase(phase);
if(!uvm_config_db#(my_uvc_cfg)::get(this,“*”,“uvc_cfg”,uvc_cfg)) begin
`uvm_fatal(get_type_name(),“I am not able to get uvc_cfg handle”);
end
endfunction : build_phase

endclass : my_sequencer

class my_base_sequence extends uvm_sequence#(my_packet);

my_packet pkt;

uvm_object_utils(my_base_sequence) uvm_declare_p_sequencer(my_sequencer)

function new(string name = “my_base_sequence”);
super.new(name);
endfunction : new

task body();
//create packet
//give some value
//send packet to driver
endtask

endclass : my_base_sequence

//In my agent I have created handle for my_sequencer
//In my env I have created agent handle
//In my test I created handle for my_base_sequence

//Now from run_phase of test I started my_base_sequence

my_base_sequence_handle.start(env.agent.my_sequencer_handle);

What uvm_warning and uvm_fatal I am getting is shown below

UVM_WARNING @ 0: reporter [TPRGED] Type name ‘my_sequencer’ already registered with factory. No string based look up support for multiple types with the same type name.
UVM_WARNING @ 0: reporter [TPRGED] Type name ‘my_uvc_cfg’ already registered with factory. No string based look up support for multiple types with the same type name.
//Then from the run_phase of test I got the below FATAL
UVM_FATAL /file_name @ 0: uvm_test_top.env.agent.my_sequencer_handle@@my_base_sequence_handle [DCLPSQ] my_pkg::my_base_sequence.m_set_p_sequencer uvm_test_top.env.agent.my_sequencer_handle.my_base_sequence_handle Error casting p_sequencer, please verify that this sequence/sequence item is intended to execute on this type of sequencer

//Interestingly if I remove `uvm_declare_p_sequencer(my_sequencer) from sequence this warnings and fatal error gets removed!! But I really require this declaration as I later may added few variables inside sequencer so that someone can update it and my sequence can use this

Can someone help me what went wrong here

2

In reply to rexjohn4u:

I have a few remarks and questions.

  1. The sequencer you are talking about is the only sequencer you have in your environment? Or do you have somewhere a virtual sequencer?
  2. For me it is not clear why you need configuration data in the sequencer. I guess you need them in the sequence. Because you want to take influence on the generation of sequence items.

Could you please explain?

3

Hi chr_sue,

First 2 warnings gone. Cause my sequencer was parameterized. I havn’t registered it with param_utils. Error is yet to solve

Going back to your queries.

  1. I dont have any virtual sequencer. Only one sequence
  2. There are plenty of scenarios where you may be using the variable value in the sequencer which is set from somewhere top. And based on this value your sequence behavior changes. Lets say a reactive sequence, which reacts up on the request put my DUT. In this case you may require it. There are plenty of other use case as well
4

Is there a way to call the testcase from command line if this particular test is parameterized?.
using +UVM_TESTNAME=<test_name>
But this test_name is parameterized (test_name#(value1,value2,value3))

5

Looks like these parameterized classes are causing this trouble. If override a parameter value as that of the default value provided in the parameterized class declaration, this error is coming.
I am still not sure why this is illegal

6

In reply to chr_sue:

Where are you setting the test parameters?
Did you try to do this from the cmd-line?
But you can define a typedef for parameterized class.

7

In reply to rexjohn4u:

Then you should have your configuration object in the sequence and not in the sequencer. This is the common way to do this.

8

In reply to rexjohn4u:

It is very difficult to debug your code with such a less information.But I have a work around
to resolve this issue and still you can have your requirement fulfilled.So you can try this out:

Inside the my_base_sequence,you can just declare your sequencer instead of p_sequencer declaration using `uvm_declare_p_sequencer.

Instead of

`uvm_declare_p_sequencer(my_sequencer)

,write it as

my_sequencer my_seqr_local_handle

When you start any sequence,m_sequencer is assigned/pointed to a sequencer on which that sequence is started. And inside uvm_declare_p_sequencer macro, that m_sequencer is cast to p_sequencer which is of type my_sequencer in your case if you use uvm_declare_p_sequencer macro.But we have used local declaration instead of `uvm_declare_p_sequencer.

So inside your base sequence body method, write is as

if(!$cast(my_seqr_local_handle,m_sequencer))
begin
// fatal error statement
end

Now you can access configuration class inside your sequence using my_seqr_local_handle instead of p_sequencer which resides in sequencer.

//To access any resource inside sequencer, use it as below in your sequence
my_seqr_local_handle.uvc_cfg

Hope this helps.