UVM Connect to develop/integrate CPU ISS which is in SC into UVM based TB

UVM
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My question is related to integrate CPU ISS (SC TLM2 wrapper around the ISS) in UVM TB using UVM Connect.
I would like to know if there is any development work available to integrate the CPU ISS (Instr set simulator)to replace a CPU sub system and run the test cases in C on ISS to verify the rest of the SOC.

Thanks in advance