Hi,
I am struggling right now with the problem to connect an SV analysis_port to SystemC using UVM Connect. So far, the following works:
- tlm_analysis_port (SC) to uvm_analysis_imp (SV) using uvmc_tlm1::connect on SV (see example sv2sc2sv),
- uvm_tlm_b_initiator_socket (SV) to simple_target_socket (SC).
I have made the SC class inherit from tlm_analysis_if and connect it. It does not work. I have used sc_export<tlm_analysis_if … It does not work. I used uvmc_tlm1::connect and uvmc_tlm::connect. The uvmc_tlm1 does not complain, but won’t work (SV → SC). The other command uvmc_tlm::connect complains at run-time that the type assignments (actual to formal) are incorrect. It complains that uvm_analysis_port is not of type uvm_base_port etc. According to the manual, analysis connections should be made via uvmc_tlm, but only uvmc_tlm1 works (in one direction, as used in the sv2sc2sv example). I have tried to use the tlm_analysis_fifo on the SC side, but uvmc_connect (SC) complains about multiple candidates (uvmc_connect for non/blocking put/get interfaces …).
I am using QuestaSim-64 10.2c_6, UVMC 2.3 and the UVM-1.1d that came with QuestaSim. UVM-1.2 did not compile with my QuestaSim (some SV syntax error). I have tried two combinations: UVMC lib + prebuilt UVM lib, UVMC + recompiled UVM lib (in the same installation directory). No differences.
Does UVMC actually support SV → SC via analysis ports? I see no example included in the documentation. If so, I could maybe provide a minimal working example.
Thanks in advance!
BR, Dominik