Uvm_config_db set and get error

UVM
, ,
1

Hi,
I have created a environment config db as below:
---------------------------------------------------------------
class env_cfg extends uvm_object;
`uvm_object_utils(env_cfg)
rand bit slave_address;
virtual spi_if spi_if;
---------------------------------------------------------------
i am setting the virtual interface for my spi interface from the top module with the below command:
---------------------------------------------------------------
uvm_config_db#(virtual spi_if)::set(null,“*”,“spi_if”,spi_if);
---------------------------------------------------------------
in my test I have created an object for config db and I get the config db details
I randomize the config db and set it back as below:
---------------------------------------------------------------
function void build_phase(uvm_phase phase);
super.build_phase(phase);
env_config = new;

	  if (!uvm_config_db #(virtual spi_if)::get(this,"","spi_if",env_config.spi_if)) begin
	  `uvm_error(get_type_name,"Cannot find SPI_IF configuration!")
	  end
      
	  //env_config.spi_if = spi_if;
	  assert(this.randomize()) else `uvm_error("BASE_TEST", "Randomization Failed");
      
	  uvm_config_db #(env_cfg)::set(this,"*","env_config",env_config );
	endfunction
	---------------------------------------------------------------
In my driver i get the interface and drive to the dut as below:
	---------------------------------------------------------------
	  function void build_phase(uvm_phase phase);
		super.build_phase(phase);

		if(!uvm_config_db#(virtual spi_if)::get(this, "", "spi_if", spi_if))
		`uvm_fatal("NOVIF",{"virtual interface must be set for: ",get_full_name(),"spi_if"});
	  endfunction: build_phase
	  
	  task run_phase(uvm_phase phase);
		`uvm_info(block,"IDLE", UVM_MEDIUM);
		spi_if.SPI_MODE = 0;
		spi_if.SS_N     = 1'b1;
		spi_if.SCLK     = 1'b1;
		spi_if.MOSI     = 1'b1;
	  endtask
	---------------------------------------------------------------

I get a null reference error as below, i am not able to understand why:
---------------------------------------------------------------
UVM_ERROR testbenches/testcases/base_test.sv(230) @ 0: uvm_test_top [base_test] Cannot find SPI_IF configuration!
UVM_FATAL testbenches/spi_agent/spi_driver.sv(26) @ 0: uvm_test_top.env.spi_ag.spi_drvr [NOVIF] virtual interface must be set for:
uvm_test_top.env.spi_ag.spi_drvrspi_if
---------------------------------------------------------------

also since i set the value again in test, will my previous value of spi_if get overridden?

Can someone please help me with this?
2

In reply to manasa-n:

What you are showing and what you are saying does not be the same.
Additionally it is not a good coding practice to use the same names for the type and the object.
This is legal but it makes the reading complicated.

I’d like to see the piece of code where you are passing the virtual interface to the config_db.
The error message is pointing you to base_test, but we do not see the code for this.
Please refine your code and post the relevant pieces of code here.

3

In reply to chr_sue:

Hi
Thank you for your reply,

I am passing the virtual interface to my config db from tb_top module(which is my top module) below is the code:

module tb_top;
import uvm_pkg::;
import ml_uvm::;

spi_if spi_if();

dut_top dut (
.reset spi_if.reset
.miso spi_if.miso
.mosi spi_if.mosi
.sclk spi_if.sclk
.ss spi_if.ss);

initial begin
uvm_config_db#(virtual spi_if)::set(null,“*”,“spi_if”,spi_if);
end
endmodule

I am creating an object to this config db in base_test(which is my test):

class base_test extends uvm_test;

virtual spi_if spi_if;
env_cfg env_config;

function void build_phase(uvm_phase phase);
super.build_phase(phase);
env_config = new;

if (!uvm_config_db #(virtual spi_if)::get(this,“”,“spi_if”,env_config.spi_if)) begin
`uvm_error(get_type_name,“Cannot find SPI_IF configuration!”)
end

assert(env_config.randomize()) else `uvm_error(“BASE_TEST”, “Randomization Failed”);

uvm_config_db #(env_cfg)::set(this,“*”,“env_config”,env_config );
endfunction

endclass

Thanks

4

In reply to manasa-n:

OK, it is still not complete, because I do not see the definition of the env_cfg. But I guess there is a data member ‘virtual spi_if spi_if’.
Performimg the uvm_config_db set is OK in the toplevel module.
In the base_test you do not need the declaration virtual spi_if spi_if;, because you have the virtual interface in the env_cfg.
I’d first randomize the env_config and then make the assignment of the virtual interface.
The question is if this exists:

env_config.spi_if
5

In reply to chr_sue:

Thank you!

I have a virtual interface as a data member.
so env_config.spi_if exists.

The issue was with the ml_pkg, it was calling run_test before the interface was even set!!!