In reply to verif_learner:
Not sure which diagram you are looking at, but most of them are not strict UML. Sometimes, only the arrows going vertical represent inheritance.
uvm_report_object IS-A uvm_object.
uvm_component IS-A uvm_report_object
uvm_report_handler IS-A uvm_object. It is NOT a uvm_report_object.
Technically, SystemVerilog does not have HAS-A relationships to other classes, but it can have references to other class objects. Extending a class always results in a IS-A relationship.
uvm_report_object HAS-A reference to uvm_report_handler