I am not able get transaction from monitor and also compare function `uvm_info or err verbosities are also not printing.
I tried debugging in monitor and SB with info sprint statement, in monitor I am able to see the sampled transaction data from interface but where as in SB I am not able to see anything.
Help me regarding this issue.
/////////////------------------------Master_Monitor_Code---------------------------///////////////////////////
class axi_master_monitor extends uvm_monitor;
`uvm_component_utils(axi_master_monitor)
virtual axi_interface.MR_MON axi_m_mon_vif;
axi_master_trans axi_m_xtn_h;
axi_master_agent_config axi_m_agnt_cfg;
//int ie;
uvm_analysis_port #(axi_master_trans) monitor_port;
extern function new(string name="axi_master_monitor", uvm_component parent);
extern function void build_phase(uvm_phase phase);
extern function void end_of_elaboration_phase(uvm_phase phase);
extern task run_phase(uvm_phase phase);
extern task collect_data();
extern task write_data();
extern task read_data();
extern function void report_phase(uvm_phase phase);
endclass
function axi_master_monitor::new(string name="axi_master_monitor", uvm_component parent);
super.new(name,parent);
monitor_port=new("monitor_port",this);
endfunction
function void axi_master_monitor::build_phase(uvm_phase phase);
super.build_phase(phase);
if(!uvm_config_db #(axi_master_agent_config)::get(this,"","axi_master_agent_config",axi_m_agnt_cfg))
`uvm_fatal("MASTER_MONITOR","can not get() axi_m_agnt_cfg from uvm_config_db")
endfunction
function void axi_master_monitor::end_of_elaboration_phase(uvm_phase phase);
axi_m_mon_vif=axi_m_agnt_cfg.axi_m_agt_cfg_vif;
endfunction
task axi_master_monitor::run_phase(uvm_phase phase);
collect_data();
endtask
task axi_master_monitor::collect_data();
forever
begin
if(axi_m_agnt_cfg.write_read_flag==2'b00)
begin
write_data();
end
else if(axi_m_agnt_cfg.write_read_flag==2'b01)
begin
read_data();
end
else if(axi_m_agnt_cfg.write_read_flag==2'b10)
begin
fork
write_data();
read_data();
join
end
end
endtask
task axi_master_monitor::write_data();
axi_m_xtn_h=axi_master_trans::type_id::create("axi_m_xtn_h",this);
fork
begin
//write_address
@(axi_m_mon_vif.master_monitor)
wait(axi_m_mon_vif.master_monitor.AWVALID && axi_m_mon_vif.master_monitor.AWREADY)
axi_m_xtn_h.AWADDR=axi_m_mon_vif.master_monitor.AWADDR;
axi_m_xtn_h.AWID=axi_m_mon_vif.master_monitor.AWID;
axi_m_xtn_h.AWLEN=axi_m_mon_vif.master_monitor.AWLEN;
axi_m_xtn_h.AWSIZE=axi_m_mon_vif.master_monitor.AWSIZE;
axi_m_xtn_h.AWBURST=axi_m_mon_vif.master_monitor.AWBURST;
`uvm_info(get_type_name(),$sformatf("axi_m_xtn_h.AWLEN=%d",axi_m_xtn_h.AWLEN),UVM_LOW);
end
//write data
begin
for(int i=0; i<=axi_m_xtn_h.AWLEN ;i++)
begin
@(axi_m_mon_vif.master_monitor)
wait(axi_m_mon_vif.master_monitor.WVALID && axi_m_mon_vif.master_monitor.WREADY)
@(axi_m_mon_vif.master_monitor)
axi_m_xtn_h.WID=axi_m_mon_vif.master_monitor.WID;
axi_m_xtn_h.WDATA[i]=axi_m_mon_vif.master_monitor.WDATA;
// axi_m_xtn_h.WSTRB[i]=axi_m_mon_vif.master_monitor.WSTRB;
end
end
//write response
begin
@(axi_m_mon_vif.master_monitor)
wait(axi_m_mon_vif.master_monitor.BREADY && axi_m_mon_vif.master_monitor.BVALID)
@(axi_m_mon_vif.master_monitor)
axi_m_xtn_h.BID=axi_m_mon_vif.master_monitor.BID;
axi_m_xtn_h.BRESP=axi_m_mon_vif.master_monitor.BRESP;
end
join
`uvm_info("MASTER_MONITOR_WRITE_CHHANLE",$sformatf("printing from MASTER_MONITOR_WRITE_CHHANLE \n %s",axi_m_xtn_h.sprint()),UVM_LOW);
monitor_port.write(axi_m_xtn_h);
`uvm_info("MASTER_MONITOR_WRITE_CHHANLE",$sformatf("printing from MASTER_MONITOR_WRITE_CHHANLE \n %s",axi_m_xtn_h.sprint()),UVM_LOW);
axi_m_agnt_cfg.axi_mon_count_h++;
endtask
task axi_master_monitor::read_data();
axi_m_xtn_h=axi_master_trans::type_id::create("axi_m_xtn_h",this);
//read_address
repeat(2)
@(axi_m_mon_vif.master_monitor);
wait(axi_m_mon_vif.master_monitor.ARVALID && axi_m_mon_vif.master_monitor.ARREADY)
axi_m_xtn_h.ARADDR=axi_m_mon_vif.master_monitor.ARADDR;
axi_m_xtn_h.ARID=axi_m_mon_vif.master_monitor.ARID;
axi_m_xtn_h.ARLEN=axi_m_mon_vif.master_monitor.ARLEN;
axi_m_xtn_h.ARSIZE=axi_m_mon_vif.master_monitor.ARSIZE;
axi_m_xtn_h.ARBURST=axi_m_mon_vif.master_monitor.ARBURST;
//read data
for(int i=0; i<=axi_m_xtn_h.ARLEN ;i++)
begin
repeat(2)
@(axi_m_mon_vif.master_monitor)
wait(axi_m_mon_vif.master_monitor.RREADY && axi_m_mon_vif.master_monitor.RVALID)
axi_m_xtn_h.RID=axi_m_mon_vif.master_monitor.RID;
axi_m_xtn_h.RDATA[i]=axi_m_mon_vif.master_monitor.RDATA;
`uvm_info(get_type_name(),$sformatf("axi_m_xtn_h.RDATA[%0d]=%d",i,axi_m_xtn_h.RDATA[i]),UVM_LOW);
axi_m_xtn_h.RRESP=axi_m_mon_vif.master_monitor.RRESP;
axi_m_xtn_h.RLAST=axi_m_mon_vif.master_monitor.RLAST;
end
monitor_port.write(axi_m_xtn_h);
`uvm_info("MASTER_MONITOR_READ_CHHANLE",$sformatf("printing from MASTER_MONITOR_READ_CHHANLE \n %s",axi_m_xtn_h.sprint()),UVM_LOW);
axi_m_agnt_cfg.axi_mon_count_h++;
endtask
function void axi_master_monitor::report_phase(uvm_phase phase);
`uvm_info(get_type_name(), $sformatf("Report: Master_Monitor_Sent %0d transactions",axi_m_agnt_cfg.axi_mon_count_h),UVM_LOW);
endfunction
////////////////--------------------------------------------------------------------
/////////////////////////---------------Scoreboard-------------------------------------/////////////////////
class axi_SB extends uvm_scoreboard;
`uvm_component_utils(axi_SB)
//master analysis fifo
uvm_tlm_analysis_fifo#(axi_master_trans)fifo_master;
uvm_tlm_analysis_fifo#(axi_master_trans1)fifo_master1;
//slave analysis fifo
uvm_tlm_analysis_fifo#(axi_slave_trans)fifo_slave;
axi_env_config m_cfg;
// xtns_compared : number of xtns compared
// xtns_dropped : calculates number of xtns failed
int xtns_compared ,xtns_dropped;
axi_master_trans xtn_master;
axi_master_trans1 xtn_master1;
axi_slave_trans xtn_slave;
extern function new(string name,uvm_component parent);
extern task run_phase(uvm_phase phase);
extern function void build_phase(uvm_phase phase);
extern function void WADDR_check_data(axi_master_trans xtn_master,axi_slave_trans xtn_slave);
extern function void WDATA_check_data(axi_master_trans xtn_master,axi_slave_trans xtn_slave);
extern function void WRESP_check_data(axi_master_trans xtn_master,axi_slave_trans xtn_slave);
extern function void RADDR_check_data(axi_master_trans xtn_master,axi_slave_trans xtn_slave);
extern function void RDATA_check_data(axi_master_trans xtn_master,axi_slave_trans xtn_slave);
extern function void report_phase(uvm_phase phase);
endclass
function axi_SB::new(string name,uvm_component parent);
super.new(name,parent);
fifo_master= new("fifo_master", this);
fifo_master1= new("fifo_master1", this);
fifo_slave= new("fifo_slave", this);
xtn_master= axi_master_trans::type_id::create("xtn_master",this);
xtn_master1= axi_master_trans1::type_id::create("xtn_master1",this);
xtn_slave= axi_slave_trans::type_id::create("xtn_slave",this);
endfunction
function void axi_SB::build_phase(uvm_phase phase);
if(!uvm_config_db #(axi_env_config)::get(this,"","axi_env_config",m_cfg))
`uvm_fatal("CONFIG","cannot get() m_cfg from uvm_config_db. Have you set() it?")
endfunction
task axi_SB::run_phase(uvm_phase phase);
forever
begin
if(m_cfg.write_read_flag==2'b00)
begin
fork
fifo_master.get(xtn_master); fifo_master1.get(xtn_master1);
fifo_slave.get(xtn_slave);
join
WADDR_check_data(xtn_master,xtn_slave);
WDATA_check_data(xtn_master,xtn_slave);
WRESP_check_data(xtn_master,xtn_slave);
end
else if(m_cfg.write_read_flag==2'b01)
begin
fork
fifo_master.get(xtn_master); fifo_master1.get(xtn_master1);
fifo_slave.get(xtn_slave);
join
RADDR_check_data(xtn_master,xtn_slave);
RDATA_check_data(xtn_master,xtn_slave);
end
else if(m_cfg.write_read_flag==2'b10)
begin
fork
fifo_master.get(xtn_master);
fifo_master1.get(xtn_master1);
fifo_slave.get(xtn_slave);
join
WADDR_check_data(xtn_master,xtn_slave);
WDATA_check_data(xtn_master,xtn_slave);
WRESP_check_data(xtn_master,xtn_slave);
RADDR_check_data(xtn_master,xtn_slave);
RDATA_check_data(xtn_master,xtn_slave);
end
end
endtask
function void axi_SB::WADDR_check_data(axi_master_trans xtn_master,axi_slave_trans xtn_slave);
begin
if(xtn_master.AWADDR==xtn_slave.AWADDR)
begin
$display("******************xtn_master.AWADDR=%0d**************xtn_slave.AWADDR=%0d",xtn_master.AWADDR,xtn_slave.AWADDR);
`uvm_info("SCOREBOARD","COMPARISION for AWADDR is SUCCESSFUL",UVM_LOW)
xtns_compared++ ;
end
else
begin
`uvm_error("SCOREBOARD","COMPARISION is MISSMATCH")
xtns_dropped++ ;
end
if(xtn_master.AWLEN==xtn_slave.AWLEN)
begin
`uvm_info("SCOREBOARD","COMPARISION for AWLEN is SUCCESSFUL",UVM_LOW)
xtns_compared++ ;
end
else
begin
`uvm_error("SCOREBOARD","COMPARISION is MISSMATCH")
xtns_dropped++ ;
end
if(xtn_master.AWSIZE==xtn_slave.AWSIZE)
begin
`uvm_info("SCOREBOARD","COMPARISION for AWSIZE is SUCCESSFUL",UVM_LOW)
xtns_compared++ ;
end
else
begin
`uvm_error("SCOREBOARD","COMPARISION is MISSMATCH")
xtns_dropped++ ;
end
if(xtn_master.AWBURST==xtn_slave.AWBURST)
begin
`uvm_info("SCOREBOARD","COMPARISION for AWBURST is SUCCESSFUL",UVM_LOW)
xtns_compared++ ;
end
else
begin
`uvm_error("SCOREBOARD","COMPARISION is MISSMATCH")
xtns_dropped++ ;
end
if(xtn_master.AWID==xtn_slave.AWID)
begin
`uvm_info("SCOREBOARD","COMPARISION for AWID is SUCCESSFUL",UVM_LOW)
xtns_compared++ ;
end
else
begin
`uvm_error("SCOREBOARD","COMPARISION is MISSMATCH")
xtns_dropped++ ;
end
end
endfunction
function void axi_SB::WDATA_check_data(axi_master_trans xtn_master,axi_slave_trans xtn_slave);
begin
for(int i=0;i<=xtn_master.AWLEN;i++)
begin
if(xtn_master.WID==xtn_slave.WID)
begin
`uvm_info("SCOREBOARD","COMPARISION for WID is SUCCESSFUL",UVM_LOW)
xtns_compared++ ;
end
if(xtn_master.WDATA[i]==xtn_slave.WDATA[i])
begin
`uvm_info("SCOREBOARD","COMPARISION for WDATA is SUCCESSFUL",UVM_LOW)
xtns_compared++ ;
end
else
begin
`uvm_error("SCOREBOARD","COMPARISION of WDATA is MISSMATCH")//uvm_error
xtns_dropped++ ;
end
end
end
endfunction
function void axi_SB::WRESP_check_data(axi_master_trans xtn_master,axi_slave_trans xtn_slave);
begin
if(xtn_master.BID==xtn_slave.BID)
begin
`uvm_info("SCOREBOARD","COMPARISION for WID is SUCCESSFUL",UVM_LOW)
xtns_compared++ ;
end
else
begin
`uvm_error("SCOREBOARD","COMPARISION of WID is MISSMATCH")
xtns_dropped++ ;
end
end
endfunction
function void axi_SB::RADDR_check_data(axi_master_trans xtn_master,axi_slave_trans xtn_slave);
begin
if(xtn_master.ARADDR==xtn_slave.ARADDR)
begin
$display("************ARADDDDDDDDDDDDDDDRRRRRRRR******%d**************%d",xtn_master.ARADDR,xtn_slave.ARADDR);
`uvm_info("SCOREBOARD","COMPARISION for ARADDR is SUCCESSFUL",UVM_LOW)
xtns_compared++ ;
end
if(xtn_master.ARLEN==xtn_slave.ARLEN)
begin
`uvm_info("SCOREBOARD","COMPARISION for ARLEN is SUCCESSFUL",UVM_LOW)
xtns_compared++ ;
end
if(xtn_master.ARSIZE==xtn_slave.ARSIZE)
begin
`uvm_info("SCOREBOARD","COMPARISION for AWSIZE is SUCCESSFUL",UVM_LOW)
xtns_compared++ ;
end
if(xtn_master.ARBURST==xtn_slave.ARBURST)
begin
`uvm_info("SCOREBOARD","COMPARISION for AWBURST is SUCCESSFUL",UVM_LOW)
xtns_compared++ ;
end
if(xtn_master.ARID==xtn_slave.ARID)
begin
`uvm_info("SCOREBOARD","COMPARISION for AWID is SUCCESSFUL",UVM_LOW)
xtns_compared++ ;
end
else
begin
`uvm_error("SCOREBOARD","COMPARISION is MISSMATCH")
xtns_dropped++ ;
end
end
endfunction
function void axi_SB::RDATA_check_data(axi_master_trans xtn_master,axi_slave_trans xtn_slave);
begin
//for(int i=0;i<=xtn_master.ARLEN;i++)
//begin
if(xtn_master.RID==xtn_slave.RID)
begin
`uvm_info("SCOREBOARD","COMPARISION for RID is SUCCESSFUL",UVM_LOW)
xtns_compared++ ;
end
/* if(xtn_master.RDATA[i]==xtn_slave.RDATA[i])
begin
`uvm_info("SCOREBOARD","COMPARISION for RDATA is SUCCESSFUL",UVM_LOW)
xtns_compared++ ;
end*/
else
begin
`uvm_error("SCOREBOARD","COMPARISION of RDATA is MISSMATCH")
xtns_dropped++ ;
end
//end
end
endfunction
function void axi_SB::report_phase(uvm_phase phase);
`uvm_info(get_type_name(), $sformatf("\n \n Number of Read Transactions Dropped : %0d \n Number of Read Transactions compared : %0d \n\n",xtns_dropped,xtns_compared), UVM_LOW)
endfunction
////////////////////--------------------------------------------------------------------------------------
//--------------------------Sim results------------------------------------------------------/////////////
# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(215) @ 0: reporter [Questa UVM] QUESTA_UVM-1.2.3
# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(216) @ 0: reporter [Questa UVM] questa_uvm::init(+struct)
# UVM_INFO @ 0: reporter [RNTST] Running test first_axi_test...
# UVM_INFO @ 0: reporter [UVMTOP] UVM testbench topology:
# --------------------------------------------------------------------
# Name Type Size Value
# --------------------------------------------------------------------
# uvm_test_top first_axi_test - @476
# axi_env_h axi_env - @499
# axi_sb_h[0] axi_SB - @649
# fifo_master uvm_tlm_analysis_fifo #(T) - @656
# analysis_export uvm_analysis_imp - @695
# get_ap uvm_analysis_port - @687
# get_peek_export uvm_get_peek_imp - @671
# put_ap uvm_analysis_port - @679
# put_export uvm_put_imp - @663
# fifo_master1 uvm_tlm_analysis_fifo #(T) - @703
# analysis_export uvm_analysis_imp - @742
# get_ap uvm_analysis_port - @734
# get_peek_export uvm_get_peek_imp - @718
# put_ap uvm_analysis_port - @726
# put_export uvm_put_imp - @710
# fifo_slave uvm_tlm_analysis_fifo #(T) - @750
# analysis_export uvm_analysis_imp - @789
# get_ap uvm_analysis_port - @781
# get_peek_export uvm_get_peek_imp - @765
# put_ap uvm_analysis_port - @773
# put_export uvm_put_imp - @757
# axi_v_sequencer_h axi_virtual_sequencer - @540
# rsp_export uvm_analysis_export - @547
# seq_item_export uvm_seq_item_pull_imp - @641
# arbitration_queue array 0 -
# lock_queue array 0 -
# num_last_reqs integral 32 'd1
# num_last_rsps integral 32 'd1
# m_collector_h1[0] master_collector1 - @824
# analysis_imp uvm_analysis_imp - @831
# m_collector_h[0] master_collector - @809
# analysis_imp uvm_analysis_imp - @816
# master_agt_top_h1[0] axi_master_agt_top1 - @522
# axi_m_agnt_h axi_master_agent1 - @861
# axi_m_drv_h axi_master_driver1 - @885
# rsp_port uvm_analysis_port - @900
# seq_item_port uvm_seq_item_pull_port - @892
# axi_m_mon_h axi_master_monitor1 - @870
# monitor_port uvm_analysis_port - @877
# axi_m_seqr_h axi_master_sequencer1 - @908
# rsp_export uvm_analysis_export - @915
# seq_item_export uvm_seq_item_pull_imp - @1009
# arbitration_queue array 0 -
# lock_queue array 0 -
# num_last_reqs integral 32 'd1
# num_last_rsps integral 32 'd1
# master_agt_top_h[0] axi_master_agt_top - @511
# axi_m_agnt_h axi_master_agent - @1024
# axi_m_drv_h axi_master_driver - @1048
# rsp_port uvm_analysis_port - @1063
# seq_item_port uvm_seq_item_pull_port - @1055
# axi_m_mon_h axi_master_monitor - @1033
# monitor_port uvm_analysis_port - @1040
# axi_m_seqr_h axi_master_sequencer - @1071
# rsp_export uvm_analysis_export - @1078
# seq_item_export uvm_seq_item_pull_imp - @1172
# arbitration_queue array 0 -
# lock_queue array 0 -
# num_last_reqs integral 32 'd1
# num_last_rsps integral 32 'd1
# s_collector_h[0] slave_collector - @839
# analysis_imp uvm_analysis_imp - @846
# slave_agt_top_h[0] axi_slave_agt_top - @533
# axi_s_agt_t_h axi_slave_agent - @1187
# axi_s_drvh_h axi_slave_driver - @1211
# rsp_port uvm_analysis_port - @1226
# seq_item_port uvm_seq_item_pull_port - @1218
# axi_s_mon_h axi_slave_monitor - @1196
# monitor_port uvm_analysis_port - @1203
# axi_s_seqrh_h axi_slave_sequencer - @1234
# rsp_export uvm_analysis_export - @1241
# seq_item_export uvm_seq_item_pull_imp - @1335
# arbitration_queue array 0 -
# lock_queue array 0 -
# num_last_reqs integral 32 'd1
# num_last_rsps integral 32 'd1
# --------------------------------------------------------------------
#
# master driver axi_m_agnt_cfg.write_read_flag=00
# master driver axi_m_agnt_cfg.write_read_flag=01
# master driver axi_m_agnt_cfg.write_read_flag=01
# UVM_INFO .\src\master_monitor1.2.sv(99) @ 30: uvm_test_top.axi_env_h.master_agt_top_h[0].axi_m_agnt_h.axi_m_mon_h [axi_master_monitor] axi_m_xtn_h.AWLEN= 1
# UVM_INFO .\src\slave_monitor.sv(111) @ 50: uvm_test_top.axi_env_h.slave_agt_top_h[0].axi_s_agt_t_h.axi_s_mon_h [axi_slave_monitor] axi_s_xtn_h.WDATA[0]=2295421533
# master driver axi_m_agnt_cfg.write_read_flag=00
# UVM_INFO .\src\slave_monitor.sv(111) @ 130: uvm_test_top.axi_env_h.slave_agt_top_h[0].axi_s_agt_t_h.axi_s_mon_h [axi_slave_monitor] axi_s_xtn_h.WDATA[1]=3751060094
# UVM_INFO .\src\slave_collector.sv(28) @ 130: uvm_test_top.axi_env_h.s_collector_h[0] [slave_collector] slave_collector coverage
# UVM_INFO .\src\slave_monitor.sv(129) @ 130: uvm_test_top.axi_env_h.slave_agt_top_h[0].axi_s_agt_t_h.axi_s_mon_h [SLAVE_MONITOR_WRITE] ***SLAVE_MONITOR_WRITE***printing from slave monitor_WRITE
# ----------------------------------------------
# Name Type Size Value
# ----------------------------------------------
# axi_s_xtn_h axi_slave_trans - @1357
# AWID integral 4 'h6
# AWADDR integral 32 'he9
# AWLEN integral 4 'h1
# AWSIZE integral 3 'h0
# AWBURST integral 2 'h0
# WDATA[0] integral 32 'h88d15a5d
# WDATA[1] integral 32 'hdf94a27e
# WDATA[2] integral 32 'h0
# WDATA[3] integral 32 'h0
# WDATA[4] integral 32 'h0
# WDATA[5] integral 32 'h0
# WDATA[6] integral 32 'h0
# WDATA[7] integral 32 'h0
# WDATA[8] integral 32 'h0
# WDATA[9] integral 32 'h0
# WDATA[10] integral 32 'h0
# WDATA[11] integral 32 'h0
# WDATA[12] integral 32 'h0
# WDATA[13] integral 32 'h0
# WDATA[14] integral 32 'h0
# WDATA[15] integral 32 'h0
# WSTRB[0] integral 4 'b0
# WSTRB[1] integral 4 'b0
# WSTRB[2] integral 4 'b0
# WSTRB[3] integral 4 'b0
# WSTRB[4] integral 4 'b0
# WSTRB[5] integral 4 'b0
# WSTRB[6] integral 4 'b0
# WSTRB[7] integral 4 'b0
# WSTRB[8] integral 4 'b0
# WSTRB[9] integral 4 'b0
# WSTRB[10] integral 4 'b0
# WSTRB[11] integral 4 'b0
# WSTRB[12] integral 4 'b0
# WSTRB[13] integral 4 'b0
# WSTRB[14] integral 4 'b0
# WSTRB[15] integral 4 'b0
# WID integral 4 'h6
# ARID integral 4 'h0
# ARADDR integral 32 'h0
# ARLEN integral 4 'h0
# ARSIZE integral 3 'h0
# ARBURST integral 2 'h0
# RDATA[0] integral 32 'h4
# RDATA[1] integral 32 'h5
# RDATA[2] integral 32 'h8
# RDATA[3] integral 32 'h7
# RDATA[4] integral 32 'h9
# RDATA[5] integral 32 'h1
# RDATA[6] integral 32 'h3
# RDATA[7] integral 32 'h2
# ----------------------------------------------
#
# UVM_INFO .\src\master_monitor1.2.sv(133) @ 170: uvm_test_top.axi_env_h.master_agt_top_h[0].axi_m_agnt_h.axi_m_mon_h [MASTER_MONITOR_WRITE_CHHANLE] printing from MASTER_MONITOR_WRITE_CHHANLE
# ------------------------------------------
# Name Type Size Value
# ------------------------------------------
# axi_m_xtn_h axi_master_trans - @1363
# AWID integral 4 'h6
# AWADDR integral 32 'he9
# AWLEN integral 4 'h1
# AWSIZE integral 3 'h0
# AWBURST integral 2 'h0
# WID integral 4 'h6
# BID integral 2 'h2
# BRESP integral 4 'h0
# ARID integral 4 'h0
# ARADDR integral 32 'h0
# ARLEN integral 4 'h0
# ARSIZE integral 3 'h0
# ARBURST integral 2 'h0
# RDATA[0] integral 32 'h0
# RDATA[1] integral 32 'h0
# RDATA[2] integral 32 'h0
# RDATA[3] integral 32 'h0
# RDATA[4] integral 32 'h0
# RDATA[5] integral 32 'h0
# RDATA[6] integral 32 'h0
# RDATA[7] integral 32 'h0
# ------------------------------------------
#
# UVM_INFO .\src\master_collector.sv(28) @ 170: uvm_test_top.axi_env_h.m_collector_h[0] [master_collector] master_collector coverage
# UVM_INFO .\src\master_monitor1.2.sv(135) @ 170: uvm_test_top.axi_env_h.master_agt_top_h[0].axi_m_agnt_h.axi_m_mon_h [MASTER_MONITOR_WRITE_CHHANLE] printing from MASTER_MONITOR_WRITE_CHHANLE
# ------------------------------------------
# Name Type Size Value
# ------------------------------------------
# axi_m_xtn_h axi_master_trans - @1363
# AWID integral 4 'h6
# AWADDR integral 32 'he9
# AWLEN integral 4 'h1
# AWSIZE integral 3 'h0
# AWBURST integral 2 'h0
# WID integral 4 'h6
# BID integral 2 'h2
# BRESP integral 4 'h0
# ARID integral 4 'h0
# ARADDR integral 32 'h0
# ARLEN integral 4 'h0
# ARSIZE integral 3 'h0
# ARBURST integral 2 'h0
# RDATA[0] integral 32 'h0
# RDATA[1] integral 32 'h0
# RDATA[2] integral 32 'h0
# RDATA[3] integral 32 'h0
# RDATA[4] integral 32 'h0
# RDATA[5] integral 32 'h0
# RDATA[6] integral 32 'h0
# RDATA[7] integral 32 'h0
# ------------------------------------------
#
# UVM_INFO verilog_src/uvm-1.1d/src/base/uvm_objection.svh(1267) @ 670: reporter [TEST_DONE] 'run' phase is ready to proceed to the 'extract' phase
# UVM_INFO .\src\axi_SB.sv(290) @ 670: uvm_test_top.axi_env_h.axi_sb_h[0] [axi_SB]
#
# Number of Read Transactions Dropped : 0
# Number of Read Transactions compared : 0
#
#
# UVM_INFO .\src\master_driver1.sv(372) @ 670: uvm_test_top.axi_env_h.master_agt_top_h1[0].axi_m_agnt_h.axi_m_drv_h [axi_master_driver1] Report: Master_Driver_Sent 1 transactions
# UVM_INFO .\src\master_monitor1.sv(184) @ 670: uvm_test_top.axi_env_h.master_agt_top_h1[0].axi_m_agnt_h.axi_m_mon_h [axi_master_monitor1] Report: Master_Monitor_Sent 0 transactions
# UVM_INFO .\src\master_driver.sv(411) @ 670: uvm_test_top.axi_env_h.master_agt_top_h[0].axi_m_agnt_h.axi_m_drv_h [axi_master_driver] Report: Master_Driver_Sent 1 transactions
# UVM_INFO .\src\master_monitor1.2.sv(186) @ 670: uvm_test_top.axi_env_h.master_agt_top_h[0].axi_m_agnt_h.axi_m_mon_h [axi_master_monitor] Report: Master_Monitor_Sent 1 transactions
# UVM_INFO .\src\slave_driver.sv(431) @ 670: uvm_test_top.axi_env_h.slave_agt_top_h[0].axi_s_agt_t_h.axi_s_drvh_h [axi_slave_driver] Report: Slave_Driver_Sent 1 transactions
# UVM_INFO .\src\slave_monitor.sv(176) @ 670: uvm_test_top.axi_env_h.slave_agt_top_h[0].axi_s_agt_t_h.axi_s_mon_h [axi_slave_monitor] Report: slave_Monitor_Sent 1 transactions
#
# --- UVM Report Summary ---
#
# ** Report counts by severity
# UVM_INFO : 20
# UVM_WARNING : 0
# UVM_ERROR : 0
# UVM_FATAL : 0
# ** Report counts by id
# [MASTER_MONITOR_WRITE_CHHANLE] 2
# [Questa UVM] 2
# [RNTST] 1
# [SLAVE_MONITOR_WRITE] 1
# [TEST_DONE] 1
# [UVMTOP] 1
# [axi_SB] 1
# [axi_master_driver] 1
# [axi_master_driver1] 1
# [axi_master_monitor] 2
# [axi_master_monitor1] 1
# [axi_slave_driver] 1
# [axi_slave_monitor] 3
# [master_collector] 1
# [slave_collector] 1
# ** Note: $finish : C:/questasim64_10.7c/win64/../verilog_src/uvm-1.1d/src/base/uvm_root.svh(430)
# Time: 670 ns Iteration: 54 Instance: /tb_top
# 1
# Break in Task uvm_pkg/uvm_root::run_test at C:/questasim64_10.7c/win64/../verilog_src/uvm-1.1d/src/base/uvm_root.svh line 430