UVM Accelerated TB (Co-Emulation)

UVM
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1

Guys,

I’m architecting an UVM accelerated TB for our SoC?

Points to be considered:

  1. Split Top into 2 tops (Synthesizable top and Class Top) and both interacts via transactions.
  2. No Timings (@, clocks, delays, wait) and pin level signals at Class hierarchy.
  3. Driver, Monitors or any component interacts to interface modules through task/function calls. (No direct contact)

Have you done previously?

Kindly share your experience, which may helps.

John

2

Hi John, we have some advice and example code in the Verification Academy Cookbook Emulation chapter, that should get you started with the testbench architecture side of things.

3

In reply to gordon:

Thanks Gordon.

John

4

Hi,

We have some VIPs which are non-accelerated. Can we use them in Co-emulation TB?

We are planning to convert them in future.

John

5

Hi John,
We don’t have an exact answer - we recommend you work with your emulation AE and the guidelines they provide for preparing your code for co-emulation - some acceleration requirements are ‘rules’ i.e. you would need to make those changes in order to use co-emulation at all, and others are ‘guidelines’ i.e. they would be highly desirable to you, from a performance point of view. Non-accelerated VIPs can become the bottleneck that prevents you getting the most out of your co-emulation solution. Good luck,