Using wait on uvm object handle passed from test to sequence

SystemVerilog
,
1

I have requirement of passing a uvm object handle from test to sequence in order to instruct sequence when/what instruction to perform.


class myInfo extends uvm_object;
  int val = 0;
endclass

class mySeq extend uvm_sequence;
  myInfo info;
  ..

  task body();
    uvm_config_db#(myInfo)::get(null, { "uvm_test_top.", seq.get_full_name()}, "info", info); // got handle, not created new one
     .. // do something
    wait(info.val == 10); // hanged here
    // do something more
  endtask;

endclass

class myTest extends uvm_test;
  myInfo info; 
  mySeq  seq;

  uvm_analysis_imp(myInfo, myTest) _exp;
.. 
  function void build_phase(uvm_phase phase);
    info = myInfo::type_id::create("myInfo");
    _exp = new("_exp", this);
  endfunction
..
  // _exp connected to env in connect phase
..
  function void write(myInfo info);
    this.info.copy(info); // here info.val becomes 10
  endfunction

  task main_phase(uvm_phase phase)
    seq = mySeq::type_id::create("mySeq");
    uvm_config_db#(myInfo)::set(this, seq.get_full_name(), "info", info);
    seq.start(null);
  endtask
endclass

Am I missing something here?
I am seeing info.val updated to 10 in test, however seq is still not progressing further.

2

In reply to bhupesh.paliwal:

Did you make self debugging? You didn’t show the full code, it’s difficult to help you solve the problem. You said that the sequence was started, sequence was stopped at “wait” instruction? And you got the correct value (equal 10) in “write” function? If so, you need to check the copy function: If you want to copy the “val” attribute in “info” object. You have to add the “val” to `uvm_field_int macro otherwise, “val” will be never get value in copy function.

Use `uvm_info to debug the problem.

Thanks,
Chris.

3

In reply to chrisle:

Thanks Chris for replying back. Yes you are right, seems I forgot to add val in `uvm_field_int macro.
Appreciate your prompt help.