In reply to bdreku:
In reply to Bibin Paul:
The `timescale compiler directive specifies the default time unit and precision for all design elements that follow this directive. It does not speed up the simulation time.
To increase the simulation time, you can use several coding tricks as given in dvcon paper “Yikes! Why is My SystemVerilog Testbench So Slooooow?”
Hi,
Could you please let me know, if I write a particular code using concurrent way or in sequential way , which will be faster/slower . ? Which has advantage over the other ? or are they both same .
Example code snippet :
Code1:
if (en)
count = count +1;
display(“new count value”)
VS:
Now lets assume the count is incrementing in some other parallel block, to display the value of count we are using a parallel thread like below .
Code2:
fork
forever @count
display(“new count value”)
join_none
Which among the 2 codes will make the simulator run faster ? if so why.
Thanks