In reply to Bibin Paul:
Time is an abstraction in Verilog simulator. If you write a clock generator with a #50 delay, it really does not matter if the #50 is 50ns or 50ps, the code it executes is the same. If you are simulating a completely RTL design, the clock is probably the only place a delay appears. Then the simulator just advances time from 0, to 50, to 100, to 150. So changing the timescale will have no effect on the simulation speed.
It starts to matter when you have many different clock rates, and introduce gates with delays, and how much precision those delays are specified. Sometimes poorly written code with combinational feedback loops can oscillate, and the relative size of the delays in the loop determines how many times it oscillates per clock cycle.
It would help to have a good understanding of how timescales work, and how delays are specified throughout your design. An inadvertent #1 placed in your code can have various consequences if you you do not understand the timescale.