Using SystemVerilog Clocking Block to verify a simple valid/ready handshaking design

In reply to markylew:
The question is not about “correctness” since ~a_bit_var produces the same result of !a_bit_var. The issue is the intent, or how it reads /visualize. When I see the “~” I visualize bit-flipping. When I see"!" I since the logical result (true/false).
As Dave said, “It should be what the intent requires. In general, I would stick with logical operators and only use bitwise on vectors greater than 1-bit wide AND the operation requires it, like masking.”