Using SystemVerilog Clocking Block to verify a simple valid/ready handshaking design

In reply to ben@SystemVerilog.us:

I really appreciate the information! It’s very helpful.

You had initially mentioned “You tend to use the bitwise instead of the logical operator”. In my response I had meant that in my code I didn’t find the use of bitwise and was asking you to indicate where I was using bitwise operator.

Thanks again.