Using SystemVerilog Clocking Block to verify a simple valid/ready handshaking design

SystemVerilog
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In reply to ben@SystemVerilog.us:

would like to move to constrained-random tests. Can you provide some guidance?

I copied into my SVA book open source code examples on constrained-randomization. The source of that book is System Verilog Functional Verification 1st Edition
by Sasan Iman (Author), Warren J. Smith (Author)
Since the examples are open-source, I am providing a link to the models.
That should help a bit. Of course, 1800’2017 has info on that too.

Ben SystemVerilog.us