In reply to Have_A_Doubt:
My intent is to know the working of the above code.
IMHO: Don’t worry about Verilog slides. Unless you are a teacher, you don’t ship PPT, you create Verilog code to make chips. Write clear, reusable Verilog code. A timescale of 10ns/1ns and delays of #1.53 are just bugs waiting to bite you.
Use a timescale of 1ns, write the delay as #15.3ns, and use $timeformat(-9, 0, “ns”, 0) to show you the resulting time in nanoseconds. Better yet, if you know that the delays are going to be rounded, use just #15ns.