Using specify blocks with for loops?

SystemVerilog
1

I am trying to model path delays for an n-bit wide signal. I can do this fine if I explicitly define the delay for each individual bit, like this (n=3):

specify
        (in_data[0] => delayed_data[0]) = 5;
        (in_data[1] => delayed_data[1]) = 2;
        (in_data[2] => delayed_data[2]) = 1;
    endspecify

However, I want to be able to specify random delays for each bit of in_data when in_data is n-bits wide. My idea was something like this:

for (n=0;n<DATA_WIDTH-1;n=n+1)
    begin
        specify
           (in_data[n] => delayed_data[n]) = {$random};
        endspecify
    end

This gives me an error: “near ‘specify’: syntax error, unexpected specify”

I also tried placing the for loop within the specify block. This resulted in the following error: “near ‘begin’: syntax error, unexpected begin, expecting endspecify”

I would really appreciate any tips on how to do this correctly

2

You cannot have a loop inside a specify block, nor can you call $random inside a specify block.

Perhaps you can explain at a higher level what you are trying to accomplish. It seems unlikely you would want to use a random number generator to perform accurate timing analysis.