Using parameter array in for loop to construct parameterized object

SystemVerilog
4

In reply to NiLu:
Yes, the race conditional is another issue whenever you have multiple initial blocks reading and writing the same variables at time 0.

You are also correct that you can’t use a generate block inside a class. But what you can do instead of constructing an array of agents inside the generate block, you use the factory to construct an array of proxies for the agent using uvm_object wrapper. It would look something like

package my_stuff;
class my_agent#(int p) extends uvm_agent;
...
endclass
uvm_object_wrapper c_array[int];
class C#(int p) extends uvm_component_registry#(my_agent#(p));
 function new;
  c_array[p] = this;
 endfunction
endclass
endpackage
module top;
  parameter N=3;
  parameter integer len[N]={5,6,7};
 
   for(genvar i=0;i<N;i++) begin      
	 my_stuff::C#(len[i]) myC=new;
   end
   initial run_test();
endmodule

Then when you go to construct your agents in the env, you can do this with i as a variable

c_array[i].create_component("name",parent);