Using $onehot in constraint block

SystemVerilog
,
1

I have a following constraint,

typedef enum {
    none_dist,
    low_dist ,
    medium_dist,
    high_dist,
    on_dist
  } test_dist_t;
rand test_dist_t b;
bit c;
constraint cst{
  a dist { 0:= 25, 1:= 75 };
  b dist {low_dist := 60, medium_dist := 35, high_dist := 5};
  c -> {
    d dist  { 0 := 25, 1 := 75 };
  }
  //Problematic constraint condition - Not working
  $onehot({a, (b != none_dist), d});
}

With the above version of constraint, variable d never goes HIGH in any one the tests. But if $onehot function is replaced as below

constraint cst{
  a dist { 0:= 25, 1:= 75 };
  b dist {low_dist := 60, medium_dist := 35, high_dist := 5};
  c -> {
    d dist  { 0 := 25, 1 := 75 };
  }
  /Working constraint condition
  a ^ (b != none_dist) ^ d;
}

Able to see d variable going HIGH on some tests. Only difference between above mentioned constraints are use of $onehot and not using $onehot.

Note: bit c is set externally.

Not able to understand the problem with the constraint that uses $onehot function because of which d never happens. Please help me debugging the constraint.

2

In reply to surya_mudgal:

The two versions of your constraints are not equivalent.

a ^ (b != none_dist) ^ d is true of one operand, or all three operands are true. That is not the same as one-hot.

b can only have the values low_dist, medium_dist, or nudist. So (b != none_dist) must always be true.

3

In reply to surya_mudgal:


$onehot({a, (b != none_dist), d});
//here, none of 'a & d' will go HIGH
//$onehot will make sure only one bit of {a, (b != none_dist), d} will be set to '1 
//(b != none_dist) will force, b to be always non-zero => a and d will always have ZERO value