Using objection mechanism from uvm_component

Hi ,

I use objection mechanism in the test as described in the cookbook . But this is not enough for me since after all sequence items were driven, the scoreboard need to wait some process time and check it . Using this approach , simulation completes with some of the data was not checked.

What I want is to raise objection in the scoreboard while there are pending comparisons

I tried the following code in the scoreboard run phase, In this approach the simulation continues to run forever.

virtual task run_phase(uvm_phase phase);
forever begin
@(packet_sent)
if (packet_array.size()==0) // check pending packets to compare
phase.drop_objection(this);
else
phase.raise_objection(this);
end
endtask

The following code works , simulation stops at the first time packet_array is empty:
virtual task run_phase(uvm_phase phase);
phase.raise_objection(this);
forever begin
@(packet_sent)
if (packet_array.size()==0) // check pending packets to compare
phase.drop_objection(this);
end
endtask

But It is wrong since i would like to be able to drop and raise objections multiple times during simulation.
I would like to use the previous option but as said - not working and the simulation is endless .

Any idea how to make it work?

Thanks!
Ilan

Use the phase_ready_to_end() method, as shown in the Cookbook.

In reply to tfitz:

Works like magic .
Thanks