Using .matched for a Multithreaded antecedent

SystemVerilog
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1

Hi ,
I was trying following code for sequence method .matched ( as source and destination clocks are different ) : edaplayground

Due to ##[1:5] oe_ , the sequence ‘RdS’ completes twice , once at T:65 and 2nd time at T:75.
Shouldn’t the antecedent should be true non-vacuously twice ? i.e once at T:75 and 2nd time at T:85.

2

In reply to MICRO_91:
Considering your example, slightly modified to add a pass/fail activated in the action block and to extend the simulation time a bit longer.
Multi-threaded sequence for .matched(1) - EDA Playground code
EPWave Waveform Viewer wave
Rules about the matched

  1. .matched status set in the Observed region
sequence  RdS ;
@(posedge  Busclk)  $fell(as_ )  ##1 rd  ##[1:5] oe_  ##0
( 1 , $display("TIME: %2t Sequence RdS Completes",$time) ) ;
endsequence
TIME: 65 Sequence RdS Completes // Call this EDP65 (endpoint)
TIME: 75 Sequence RdS Completes // Call this EDP75
We have 2 end points,
The EDP65 .matched end point is set at t65
The EDP75 .matched end point is set at t75
  1. The matched end point persists until the Observed region of the
    1st clock tick of the destination sequence after the match (i.e., after the .matched end point)
property  checkP ;
@(negedge sysclk) ( RdS.matched , $display("TIME: %2t  RdS.matched ",$time) ) |=>  rdDataLatch  ##0  ( $isunknown(data)  ==  0  )   ; endproperty
For EDP65 the 1st clock tick of the destination sequence after the match is at t75 at the
(negedge sysclk)
For EDP75 the 1st clock tick of the destination sequence after the match is at t85 at the (negedge sysclk)
TIME: 75  RdS.matched   // sim results
TIME: 85  RdS.matched
  1. The .matched results is for use at arrival of that 1st clock tick of the destination sequence after the match
    (i.e., available for use at RdS.matched)

If we used |-> instead of |=>, then with EDP65 being matched at t75 with the negedge sysclk, rdDataLatch will be evaluated at t75,
and because of the ##0 that follows it, you would have a pass or fail at t75.
However, in this model, we have a|=> instead of a |->. Thus, rdDataLatch is evaluated 1 clock tick later than the match (i.e, 1 cycle after the RdS.matched)
For EDP65 that occurs at t85. Since ##0  ( $isunknown(data)  ==  0  you have a PASS at t85
For EDP75 that occurs at t95. Since ##0  ( $isunknown(data)  ==  0  you have a PASS at t95

Ben Cohen
Ben@systemverilog.us
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Getting started with verification with SystemVerilog

3

In reply to ben@SystemVerilog.us:

Thanks Ben,
So there should ideally be 2 threads where the antecedent is true i.e “RdS.matched” should occur twice . Once at T:75 and 2nd one at T:85.

( Some tools show only 1 “RdS.matched” , hence I raised the question )

Also using first_match in sequence ‘RdS’ ensures that we observe “RdS.matched” only once at T:75

4

In reply to MICRO_91:

There should be 2 threads. In your initial TB, your simulation was too short.
As you know, we don’t discuss tools in this forum.

Since it is easier to analyze waveforms, I recommend that you pass in the action block an increment of variables pass/fail (as I did). Use the display as a last resort for documentation.
Ben