In reply to ben@SystemVerilog.us:
Thanks Ben,
So there should ideally be 2 threads where the antecedent is true i.e “RdS.matched” should occur twice . Once at T:75 and 2nd one at T:85.
( Some tools show only 1 “RdS.matched” , hence I raised the question )
Also using first_match in sequence ‘RdS’ ensures that we observe “RdS.matched” only once at T:75