Using int'($pow) in constraint

SystemVerilog
,
1 

Can we use int'($pow) in constraint ? Any LRM reference to the usage. 
module tb();

class power_of_2;

 rand int pos;
 rand int result;

 constraint c1 { 
   pos inside {[0:9]};
   result == int'($pow(2,pos));
 }

endclass : power_of_2

initial begin 
  power_of_2 power_of_2_h = new();
  power_of_2_h.randomize();
  $display("result : %0d",power_of_2_h.result);
end

endmodule
2

In reply to uvm_novice:

$pow() is not supported in constraints. Instead you can use “**”.

module tb();
 
class power_of_2;
 
 rand int pos;
 rand int result;
 
 constraint c1 { 
   pos inside {[0:9]};
//    result == int'($pow(2,pos));
   result == int'(2**pos);

 }
 
endclass : power_of_2
 
initial begin 
  power_of_2 power_of_2_h = new();
  power_of_2_h.randomize();
  $display("pos : %0d  |  result : %0d",power_of_2_h.pos, power_of_2_h.result);
end
 
endmodule