Using assertion to detect glitch?

SystemVerilog
, ,
4

In reply to javatea:
A few comments:

  1. I fail to undestand your “[*1:$]” in the following assertion:

property glitch_p;
realtime first_change;
realtime duration = 10;
@(a)
// detecting every 2 changes duration
(1, first_change = $realtime) |=> (($realtime - first_change) >= duration))[*1:$]; // ??
endproperty

It states that at every edge of “a” you start a new thread, and in that thread, from then on, and and forever, every edge of “a” must be >= duration. That creates multiple, unneeded threads. I strongly suggest that you read my paper
https://verificationacademy.com/forums/systemverilog/paper-understanding-sva-engine-simple-alternate-solutions
Abstract: Understanding the engine behind SVA provides not only a better appreciation and limitations of SVA, but in some situations provide features that cannot be simply implemented with the current definition of SVA. This paper first explains, by example, how a relatively simple assertion example can be written without SVA with the use of SystemVerilog tasks; this provides the basis for understanding the concepts of multithreading and exit of threads upon a condition, such as an error in the assertion. The paper then provides examples that uses computational variables within threads; those variables can cause, in some cases, errors in SVA. The strictly emulation model with tasks solves this issue.
2. On realtime, SystemVerilog is laxed and allows to specify a time in integer. From my roots in VHDL, and I prefer to specify a realtime variable with a real number
3. Add timeunits

Below is my corrected code. I believe that this is more of what you are looking for. DO NOT use the [*1:$], it serves no purpose, except overload your simulator.


import uvm_pkg::*; `include "uvm_macros.svh" 
module top; 
	timeunit 1ns; timeprecision 100ps; 
	bit clk, a, b, signal;  
	default clocking @(posedge clk); endclocking
	initial forever #10 clk=!clk;
	realtime duration=45.0ns; 
	
  property glitch_p;
    realtime first_change;
    // realtime duration = 10;
   @(signal)  // pos and neg edge 
      // detecting every 2 changes duration
     (1, first_change = $realtime) |=> (($realtime - first_change) >= duration); // [*1:$];
  endproperty
  ap_glitch_p: assert property(glitch_p);  
 
  always_ff  @(posedge clk)  begin 
 end 

 initial begin 
     repeat(200) begin 
       @(posedge clk);   
       if (!randomize(signal)  with 
           { signal dist {1'b1:=1, 1'b0:=3};
             b dist {1'b1:=1, 1'b0:=2};

           }) `uvm_error("MYERR", "This is a randomize error")
       end 
       $stop; 
    end 
endmodule

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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