In reply to ben@SystemVerilog.us:
Hi Ben ,
The key to understanding multiclocking is to understand that a clock flow into a parenthesized (or declared) sequence, but it does not flow out of it. I explain clock flow in my book.
I do understand this part .
However I am still not clear on the concept of missing leading clock for :
sequence mclocks ;
@(posedge clk1) B and @(posedge clk2) C ; // Could be "or" operator as well
endsequence
ap0:assert property ( mclocks ) ; // Compilation Error ::
// Tool1 => Error-[SVA-SLCE] Single leading clock expected
// Tool2 => xmvlog: *E,CLKSVA : The clock for a concurrent assert statement must be completely specified.
Please correct me if my following understanding in incorrect :
As you mentioned : " The and, or sequence operators require that both sequence start at the same time "
My confusion : Is above quote related to leading clock ?
(1) Legal Case :
sequence mclocks1 ;
@(posedge clk1) B and C ; // Could be "or" operator as well
endsequence
ap1:assert property ( mclocks1 ) ;
Here both sequence starts at same time i.e on posedge of clk1 which is basically the leading clock
(2) Illegal Case :
sequence mclocks ;
@(posedge clk1) B and @(posedge clk2) C ; // Could be "or" operator as well
endsequence
ap0:assert property ( mclocks ) ;
Here both sequences don’t start at the same time i.e missing leading clock
Whereas when I write :
ap2:assert property ( @(posedge clk0) A |=> mclocks ) ; // posedge of clk0 is the leading clock
Here both sequences start at the same time i.e nearest posedge of clk1 and clk2 after the antecedent is True on posedge of clk0 .