In reply to ben@SystemVerilog.us:
Hi Ben ,
(1) I am intrigued by the concept of leading clock in a multi clocked sequence and seek your assistance for the same .
Here’s what I have noted via various trial and error :
The and, or sequence operators require that both sequence start at the same time
Generally when we write :
assert property ( @( posedge clk ) B and C ) ;
Here both B and C are evaluated on each posedge of clk i.e both sequence start at the same time i.e on posedge of clk
Whereas in the top multi clocked sequence :
assert property ( @(posedge clk1) B and @(posedge clk2) C ) ;
Here there exists ambiguity whether the variables B and C start evaluation on posedge of clk1 OR at posedge of clk2
**i.e sequence don't necessarily start at the same time**
On changing code to :
ap1:assert property ( @(posedge clk0) A |=> mclocks ) ;
Now variables B and C start at the same time i.e subsequent posedge of clk1 and clk2 respectively **after the antecedent is True on leading clock ( clk0 )**
(2) When trying the following :
ap2:assert property ( @(posedge clk0) mclocks );
ap3:assert property ( @(posedge clk1) mclocks );
ap4:assert property ( @(posedge clk2) mclocks );
I still observe Compilation Error : [edalink](https://www.edaplayground.com/x/Vnr9)
I believe this is due to the clk0 / clk1 / clk2 ( mentioned in the assert property ) getting overridden by clk1 for B and clk2 for C ( within the sequence ) .
So the equivalent expression remains the same :
ap2:assert property ( mclocks );
ap3:assert property ( mclocks );
ap4:assert property ( mclocks );