In reply to MICRO_91:
The and, or sequence operators require that both sequence be true and start at the same time.
sequence mclocks ;
@(posedge clk1) B and @(posedge clk2) C ; // Could be "or" operator as well
endsequence
ap0:assert property ( mclocks ) ; // Illegal , but why ?
// Here the leading clocking event is not clearly defined.
// Is it @(posedge clk1), or is it @(posedge clk2)
// However, with
ap1:assert property ( @(posedge clk0) A |=> mclocks ) ; // Legal
// It is equivalent to
ap1:assert property ( @(posedge clk0) A |=> @(posedge clk1) B and @(posedge clk2) C);
// @(posedge clk0) flows into both "and" sequences, thus equivalent to
ap1:assert property ( @(posedge clk0) A |=>
@(posedge clk0) ##0 @(posedge clk1) B and
@(posedge clk0) ##0 @(posedge clk2) C);
// BTW, this would have been legal too.
ap0:assert property ( @(posedge clk0) mclocks );
ap0:assert property ( @(posedge clk1) mclocks );
ap0:assert property ( @(posedge clk2) mclocks );
Ben Cohen
Ben@systemverilog.us
Link to the list of papers and books that I wrote, many are now donated.
or Links_to_papers_books - Google Docs
Getting started with verification with SystemVerilog
Free URL Shortener | Powered by Rebrandly