Using ##0 Clock delay with Implication Operators

SystemVerilog
,
3

In reply to ben@SystemVerilog.us:

Hi Ben ,
I do understand the working without using ##0 in the consequent .
Does the addition of ##0 change the behavior compared to without it ?
Can I say that the below property expressions are equivalent ?


 property  multi_clocks1 ;
    @(posedge clk0) A |=> ##0 @(posedge clk1) B;
 endproperty
 
 property  multi_clocks2 ;
    @(posedge clk0) A |=> @(posedge clk1) B; // Without ##0 in consequent
 endproperty

  // [Q1]  Are  multi_clocks1 and multi_clocks2 equivalent ?

Similarly


 property  multi_clocks3 ;
    @(posedge clk0) A |-> ##0 @(posedge clk1) B;
 endproperty
 
 property  multi_clocks4 ;
    @(posedge clk0) A |-> @(posedge clk1) B; // Without ##0 in consequent
 endproperty

 // [Q2]  Are  multi_clocks3 and multi_clocks4 equivalent ?