Using ##0 Clock delay with Implication Operators

SystemVerilog
,
2

In reply to MICRO_91:
Consider the following 2 cases :


// CODE 1 : Using Non-Overlapping Implication :
    @(posedge clk0) A |=> @(posedge clk1) B;
 // CODE 2 : Using Overlapping Implication :
    @(posedge clk0) A |-> @(posedge clk1) B;
// **** (a) posedge of clk0 occurs at t0 whereas posedge of clk1 is false at t0 :
// If 'A' is true at T:t0 , when would 'B' be evaluated ?
// [Ben] Code 1: B is evaluated at the next posedge clk1
//       Code 2: B is evaluated at the next posedge clk1

// **** (b) Both posedge of clk0 and clk1 overlap at t1 :
// If 'A' is true at T:t1 , when would 'B' be evaluated ?
// [Ben] Code 1: B is evaluated at the next posedge clk1
//       Code 2: B is evaluated at the current posedge clk1, which is 
//               the same time step as posedge clk0

Ben Cohen
Ben@systemverilog.us
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