Use variable for the delay in assign statement

SystemVerilog
1

I have a piece of code like below. but it failed at syntax error. any help is appreciate.



bit clk;
initial begin
     clk = 0;
     forever begin
         #(10.0ns) clk = ~clk;
     end
end
function realtime gen_rand_delay();
    int t = {$random()} % 6;
    realtime dly;
    case (t)
        0 : begin
            dly = 0.0ns;
        end
        1 : begin
            dly = 1.0ns;
        end
        2 : begin
            dly = 2.0ns;
        end
        3 : begin
            dly = 3.0ns;
        end
        4 : begin
            dly = 4.0ns;
        end
        5 : begin
            dly = 5.0ns;
        end
    endcase
    return dly;
endfunction : gen_rand_delay

assign my_clk = #(gen_rand_delay()) clk;
2

In reply to zz8318:
the following worked for me. I provide 3 versions for the delays and the assign.
The use of the randomize gives you more options.


module top; 
    timeunit 1ns/100ps;
    `include "uvm_macros.svh"
     import uvm_pkg::*;
     bit clk, a, b, my_clk, my_ck2; 
     int v, v2, v3;   
     initial begin
       clk = 0;
       forever begin
         #(10.0ns) clk = ~clk;
         v=gen_rand_delay();
         v2=gen_rand_delay2();
         v3=gen_rand_delay3();
       end
    end
function realtime gen_rand_delay2();  // <--- UPDATED 
    automatic int t = {$random()} % 6;
    //realtime fly; // CORRECTION 
    /*case (t)
        0 : begin
            dly = 0.0ns;
        end
        1 : begin
            dly = 1.0ns;
        end
        2 : begin
            dly = 2.0ns;
        end
        3 : begin
            dly = 3.0ns;
        end
        4 : begin
            dly = 4.0ns;
        end
        5 : begin
            dly = 5.0ns;
        end
    endcase */
    return t * 1ns;   // CORRECTION 
endfunction : gen_rand_delay2

function realtime gen_rand_delay2();
    automatic int t = {$random()} % 6;
    realtime dly;
    /*case (t)
        0 : begin
            dly = 0.0ns;
        end
        1 : begin
            dly = 1.0ns;
        end
        2 : begin
            dly = 2.0ns;
        end
        3 : begin
            dly = 3.0ns;
        end
        4 : begin
            dly = 4.0ns;
        end
        5 : begin
            dly = 5.0ns;
        end
    endcase */
    return dly * 1ns;
endfunction : gen_rand_delay2

function realtime gen_rand_delay3();
    int t;     
    realtime dly;
    if (!randomize(t)  with 
         { {t>0};
           {t<=5};
         }       
             //{ a dist {1'b1:=1, 1'b0:=1};
             //  b dist {1'b1:=1, 1'b0:=2};  
        ) `uvm_error("MYERR", "This is a randomize error");
    return dly * 1ns;
endfunction : gen_rand_delay3

 
//assign  #gen_rand_delay() my_clk = clk;
assign  #v my_clk = clk;
assign  #v2 my_clk2 = clk;
assign  #v3 my_clk3 = clk;
     
       initial begin 
         repeat(200) begin 
             @(posedge clk);   
             if (!randomize(a, b)  with 
             { a dist {1'b1:=1, 1'b0:=1};
               b dist {1'b1:=1, 1'b0:=2};  
         }) `uvm_error("MYERR", "This is a randomize error");
         end 
         $finish; 
        end  
 endmodule

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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  4. FREE BOOK: Component Design by Example … A Step-by-Step Process Using VHDL with UART as Vehicle | Verification Academy
3

In reply to zz8318:

Let me add to Ben’s explanation on what the original problems with your code were.

  • You had the delay in the wrong spot for the continuous assign statement.
  • You had an illegal variable declaration for t inside function gen_rand_delay(). You need to do something different if you want a new value for t every time the function gets called. See this.
  • You also need to be more specific about when or if you want a new delay calculated.