Use uvm vip in verilog test bench

UVM
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1

Hello,

I’m making a uvm_component as a VIP in my uvm test environment.
Now, I need to reuse this component in verilog test bench. I guess I need to build a verilog wrapper for this uvm component or there are other ways.
If possible could you please recommend the appropriate methods ?

Thanks.

2

In reply to mydung:

Simple Verilog does not know anything about classes. I guess your UVC is class-based. Right?
You should consider this.
But there might be ways to bring both worlds together.
But then you have to elaborate a little bit more about your Verilog testbench.