In reply to saketa:
Please look to the initial block of the module top:
initial begin
environment = new(“env”);
// Put the interface into the resource database.
uvm_resource_db#(virtual SDM_if)::set(“env”, “SDM_if”, dut.SDM_if1);
uvm_resource_db#(virtual sine_if)::set(“env”, “sine_if”, sin_voltage_gen.sine_if1);
clk_1mhz = 0;
run_test();
end
The values of the interfaces are wrong. They should be
SDM_if1 instead of dut.SDM_if1
sine_if1 instead of sin_voltage_gen.sine_if1