In reply to dave_59:
Dave: Here it is the whole code:
import uvm_pkg::*;
import math_pkg::*;
`include "uvm_macros.svh"
//----------------
// environment env
//----------------
class env extends uvm_env;
virtual SDM_if m_if;
virtual sine_if si_if;
function new(string name, uvm_component parent = null);
super.new(name, parent);
endfunction
function void connect_phase(uvm_phase phase);
`uvm_info("LABEL", "Started connect phase.", UVM_HIGH);
// Get the interface from the resource database.
assert(uvm_resource_db#(virtual SDM_if)::read_by_name(
get_full_name(), "SDM_if", m_if));
`uvm_info("LABEL", "Finished connect phase.", UVM_HIGH);
// assert(uvm_config_db #(virtual SDM_if)::set(this, "*", "m_if", m_if));
//`uvm_info("LABEL", "Finished connect phase.", UVM_HIGH);
assert(uvm_resource_db#(virtual sine_if)::read_by_name(
get_full_name(), "sine_if", si_if));
//assert(uvm_config_db #(virtual sine_if)::set(this, "*", "si_if", si_if));
`uvm_info("LABEL", "Finished connect phase.", UVM_HIGH);
endfunction: connect_phase
task run_phase(uvm_phase phase);
phase.raise_objection(this);
`uvm_info("LABEL", "Started run phase.", UVM_HIGH);
begin
int reset_n = 0;
@(m_if.cb);
m_if.cb.Ain <= si_if.sine_out;
// m_if.cb.reset_n <= reset_n;
repeat(2) @(m_if.cb);
end
`uvm_info("LABEL", "Finished run phase.", UVM_HIGH);
phase.drop_objection(this);
endtask: run_phase
endclass
//-----------
// module top
//-----------
module top;
bit clk_1mhz;
real sine_out;
SDM_if SDM_if1();
sine_if sine_if1();
env environment;
sdm_rnm dut(SDM_if1);
sv_ams_sin_voltage_gen sin_voltage_gen(sine_if1);
initial begin
environment = new("env");
// Put the interface into the resource database.
uvm_resource_db#(virtual SDM_if)::set("env",
"SDM_if", dut.SDM_if1);
uvm_resource_db#(virtual sine_if)::set("env",
"sine_if", sin_voltage_gen.sine_if1);
clk_1mhz = 0;
run_test();
end
initial begin
forever begin
#(50) clk_1mhz = ~clk_1mhz;
end
end
initial begin
// Dump waves
$dumpvars(0, top);
end
endmodule
// SDM2 module
module sdm_rnm (SDM_if SDM_if2 );
parameter real clk_vth=0.9;
parameter alpha = 0.5;
parameter beta = 0.5;
real int1_out; /// variable-- not connection with the outside world
real int2_out;
real dac_out;
real mix1_out;
real mix2_out;
real t_int1_out;
real t_int2_out;
real sdm_out;
initial begin
int1_out = 0.0 ;
int2_out = 0.0 ;
dac_out = 0.0 ;
mix1_out = 0.0 ;
mix2_out = 0.0 ;
sdm_out = 0 ;
t_int2_out = 0 ;
t_int1_out = 0 ;
end
always @(negedge(SDM_if2.clk_1mhz))
begin
mix2_out = int1_out - dac_out ;
int2_out = t_int2_out + beta*mix2_out ;
t_int2_out = int2_out ;
mix1_out = SDM_if2.Ain - dac_out ;
int1_out = t_int1_out + alpha*mix1_out ;
t_int1_out = int1_out ;
if (int2_out >= 0.0) begin
sdm_out = 1.8 ; // ADC-- comparator
end
else if (int2_out <= 0.0)
begin sdm_out = 0 ;
end
if (sdm_out == 0) begin dac_out = 0.5 ;
end
else dac_out = 1.3 ;
SDM_if2.Dout = sdm_out ;
end
endmodule
//---------------------------------------
// Interface for the DUT
//---------------------------------------
interface SDM_if(input bit clk_1mhz, input real Ain, output bit Dout);
clocking cb @(negedge clk_1mhz);
output Ain;
input Dout;
endclocking // cb
endinterface: SDM_if
//---------------
// Interface bind
//---------------
//bind sdm_rnm SDM_if SDM_if_if0(
// .clk_1mhz(clk_1mhz),
// .Ain(Ain),
// .Dout(Dout),
// .reset_n(reset_n)
//);
//bind sv_ams_sin_voltage_gen sine_if sine_if_if0(
// .clk_1mhz(clk_1mhz),
// .sine_out(sine_out)
//);
module sv_ams_sin_voltage_gen(sine_if sine_if2);
parameter sampling_time = 5;
const real pi = 3.1416;
real time_us, time_s ;
bit sampling_clock;
real freq = 20;
real offset = 2.5;
real ampl = 2.5;
always sampling_clock = #(sampling_time) ~sampling_clock;
always @(sampling_clock) begin
time_us = $time/1000;
time_s = time_us/1000000;
end
assign sine_if2.sine_out = offset + (ampl * sin(2*pi*freq*time_s));
endmodule
interface sine_if(input bit clk_1mhz, output real sine_out);
clocking cb @(posedge clk_1mhz);
input sine_out;
endclocking
endinterface: sine_if
This code does not elaborate (when lanching simulation): Error: (vopt-7052) D:/sigma_delta_SV/FirstSDM.sv(75): Failed to find ‘SDM_if1’ in hierarchical name ‘/dut/SDM_if1’
** Error: (vopt-7052) D:/sigma_delta_SV/FirstSDM.sv(77): Failed to find ‘sine_if1’ in hierarchical name ‘/sin_voltage_gen/sine_if1’.
but when delating
environment = new("env");
// Put the interface into the resource database.
uvm_resource_db#(virtual SDM_if)::set("env",
"SDM_if", dut.SDM_if1);
uvm_resource_db#(virtual sine_if)::set("env",
"sine_if", sin_voltage_gen.sine_if1);
it elaborate and begin simulation, and there where the sin library is not found
Any help from your side will be appreciated