Use of SCE-MI for UVM based TB

UVM
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1

Hi,

I am building Tbx model for UVM test bench,
Have divided Transactor in to diver proxy which will stay on Tb side & call task which implemented on Driver BFM(sythesizable interface at HDL-Emulator side)
I have tried to for implementing it through SCE-MI 2.0 & TLM FIFO but not able to do so.
Is it possible to use SCEMI-2.0 & TLM FIFO for UVM test bench for Co-Emulation ?
Have gone through SCE-MI doc explaining about HVL side implementation for System verilog based TB but not getting much idea…Please somebody give me brief idea for implementation.

Thanks in advance,
Sundaram Dodia

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In reply to sundaram@emupro.com:

Hi Sundaram ,
Look for Chapter “Accelerating System Verilog Testbenches” in TBX user guide . That will be help full.
In my company for SV UVM TB ,we are using Mentor supprted VIF/TIF approach which is very simple and we have implemented successfully in many projects.
For SC kind of TB , I would suggest Scemi DPI is easy . And you also need to take care of kind of commn channel , Reactive or Streaming .
If Reactive , then implement using : DPI or VIF/TIF
if Streaming then better use SceMi Pipe .

Thanks,
Piyush

3

In reply to piyush:

Hi Piyush,

Thanks for your suggestion,
I have already built model ,where have used the same approach as of explained in TBX doc & its working fine.
But thinking to enhance the Emulation run time & speed by pre-fetching transactor by means of TLM FIFO & SCE-MI techniques.

Thanks
Sundaram

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In reply to sundaram@emupro.com:

OK , we are doing some experiment with SceMi PIPE so don;t have any data till now. But on theory , PIPE based approach certainly help in performance improvement.
For TLM FIFO ,I suppose it would be adding more comlexity and loosing controlability …( pasting part of Scemi 2.2 pdf )

Here is a small listing that tries to compare and contrast the semantics of FIFOs vs. pipes:
FIFOs
• Follow classical Accellera Systems Initiative’s SystemC-TLM like FIFO model
• User specified fixed sized buffer depth
• Automatic synchronization
• Support blocking and non-blocking put/get operations
• “Under the hood” optimizations possible - batching
• No notion of a flush

Pipes
• Follows Unix stream model (future/past/present semantics)
• Implementation specified buffer depth
• User controlled synchronization
• Makes concurrency optimization more straightforward
• Support only blocking operations (for determinism)
• “Under the hood” optimizations possible - batching, concurrency
• More naturally supports data shaping, vlm, eom, flushing

Thanks,
Piyush